As next generation system architectures transition from parallel bus to high performance serial interconnect architectures, to provide required performance enhancements, gigabit serdes integration in Platform ASICs has received much interest. In this key note presentation, Mr. Sangha, LSI Logic director of CoreWare IP marketing, discusses how current and future technology offerings address the industry’s needs.

D&R has as mission to promote IP based design practices around the world, to assist the IP/SoC community to define and establish best practices, to offer relevant services and technology, and finally to trigger IP based business.
Along the 7 last years D&R delivered various services to the IP/SoC community for this purpose while following the evolution and progresses made in the reuse field.
D&R presents in this keynote talk an overview and state of the art of these services mainly devoted to IP publishing, IP cataloguing, IP packaging and IP delivery.
D&R strongly supports standardized exchange practices and contributes strongly by adding its 7 years of experience.

Value is the single most important aspect of IP business transactions. But how do we assess and quantify the value of IP? This interactive panel of IP users and vendors will discuss this important question.

Moderated by: Jim Tully, VP Semiconductors, Gartner Dataquest

Panel Members:
- Jim Venable, Director, Storage Products Business Unit, Mentor Graphics
- Phil Dworsky, Director of Marketing, DesignWare IP, Synopsys
- Peter Hirt, Manager IP Procurement, STMicroelectronics
- Bart de Loore, VP and GM, CTO Reuse Technology, Philips Semiconductors
- Chris Lennard, ESL Technical Marketing Manager, ARM Ltd.

The task of verification is increasing exponentially in difficulty and the amount of engineering effort required. Just as designers have been using more, and more complex, silicon IP to rapidly assembly SoCs, they're turning to verification IP to assemble their verification environments and find more bugs, faster. This expert panel of verification IP providers, designers, and industry analysts will discuss the current state of verification IP. What's working, what's not? Who are the players? How is verification IP being used? What are the latest technologies? What's next?

Moderator: Michael Santarini, Sr. Editor, EDA and cores, EETimes

With the participation of:
- Laurent Ducousso, Verification Manager, Home Entertainment Group, STMicroelectronics
- Phil Dworsky, Director of marketing, DesignWare IP, Synopsys
- Wolfgang Ecker, Infineon
- Aleksandar Randjic, Verification IP Developer, HDL Design House