|
 |
|
HDL DH eVC are developed by dedicated team of design and verification experts. Carefully balancing structure of development team by combining design and verification engineering resources and defining proprietary eVC development methodology HDL DH provide first time success and smooth integration of eVC in customer verification environment. HDL DH eVC program is currently focused on emerging standards such as: SATA, SAS, HyperTransport, RapidIO, ...
Learn more about HDL Design Verification IPs
|
|
|
The task of verification is increasing exponentially in difficulty and the amount of engineering effort required. Just as designers have been using more, and more complex, silicon IP to rapidly assembly SoCs, they're turning to verification IP to assemble their verification environments and find more bugs, faster.
This expert panel of verification IP providers, designers, and industry analysts will discuss the current state of verification IP. What's working, what's not? Who are the players? How is verification IP being used? What are the latest technologies? What's next?
Moderator
Michael Santarini, Sr. Editor, EDA and cores, EETimes
Panelists
Phil Dworsky, Director of marketing, DesignWare IP,
Synopsys
Phil Dworsky joined Synopsys in 1993 and is currently the director of
marketing for DesignWare IP. Previous to his current responsibilities,
Mr. Dworsky held management positions in marketing, technical marketing
and corporate applications at Synopsys, most recently as director of
applications.
Mr. Dworsky came to Synopsys from Performance Processors where he was
co-founder and principal engineer. Before that, he was a co-founder of
Silicon Solutions/Zycad. He started his career at Hewlett-Packard as a
hardware and software designer. He holds a Bachelor of Science degree
with high honors in EECS (electrical engineering and computer science)
from Princeton University.
Laurent Ducousso, Verification Manager, Home Entertainment Group,
STMicroelectronics
- Responsible for Verification IP & methodology
- Manager of verification for Set-top box, DVD, and digital TV application
subsystems
Aleksandar Randjic, Verification IP Developer, HDL Design House
Aleksandar Randjic is
Verification IP developer,
Module & system-level verification engineer and
ASIC designer
Wolfgang Ecker, Infineon
Wolfgang Ecker is principal verification engineer and he is responsible for:
- innovation in field of functional verification
- system-level design
- SystemVerilog introduction at Infineon
To display this presentation RealAudio plugin is required. Get RealAudio Plugin
| 
