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EVE and CoWare Forge Strategic Alliance (Jan. 21, 2008)
EVE and CoWare today announced a strategic alliance to provide design teams with an integrated approach that ties hardware/software co-verification from EVE with SystemC virtual platforms developed with CoWare’s ESL 2.0 solutions. |
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CoWare and STARC Integrate SystemC TLM Methodology (Jan. 21, 2008)
CoWare announced the collaboration with STARC to support CoWare’s open SystemC modeling library APIs for the creation of reusable virtual platforms for architecture design and software development. |
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Esterel Studio, adopted at STMicroelectronics, enhances productive design for STBus and STNoC based control-intensive IP (Jan. 18, 2008)
Esterel EDA Technologies today announced that STMicroelectronics has applied Esterel Studio for the design of new components for the STBus and ST Network-on Chip (STNoC) within ST’s On-Chip Communication Systems (OCCS) team. |
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Synfora Integrates PICO Express with CoWare ESL 2.0 Solutions (Jan. 16, 2008)
Joint customers will use Synfora’s PICO Express to create synthesizable RTL and the corresponding transaction-level SystemC models from an untimed C algorithm for product-specific intellectual property (IP), and reuse them in combination with other ESL models in CoWare’s Platform Architect to capture the entire product platform at the system-level. |
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Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker (Jan. 14, 2008)
Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct |
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Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling (Dec. 04, 2007)
SystemC users urged to provide feedback on TLM-2 Draft 2 by January 31st |
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Synplicity Joins Xilinx ESL Design Ecosystem (Nov. 26, 2007)
The Synplify DSP environment facilitates high-level modeling and hardware abstraction, constraint-driven algorithm synthesis into RTL and powerful system-wide optimizations for performance, area, and multi-channelization tradeoff exploration. |
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CoWare and Tensilica Integrate Diamond Standard 106Micro with CoWare ESL 2.0 Technology (Nov. 20, 2007)
The integration provides designers with the first and most productive ESL 2.0 solution for platform architecture design, platform verification, and software development using Tensilica’s processor core with the smallest area, lowest power, and highest performance on the market. |
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Virtutech Accelerates and Streamlines Development of Applications for Next-Generation of IBM PowerPC Processor Cores (Nov. 14, 2007)
Virtutech today announced that its Simics™ product has been selected by IBM to create advanced, system-level simulation models for IBM’s next-generation embedded processor cores, beginning with the PowerPC 464FP core. |
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Carbon Design Systems Adds Support for Latest Version of ARM Tools (Nov. 12, 2007)
Its Carbon Model Studio generates hardware-accurate software models that integrate into RealView SoC Designer 7.0 release for rapid development and assembly of virtual platforms to explore architectural tradeoffs and perform pre-silicon software development. |
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Verification Library Accelerates OCP System Designs (Nov. 02, 2007)
JEDA Technologies today announced the availability of OCPchecker, a system-level verification library for Open Core Protocol (OCP) based system designs in SystemC. |
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CoWare and Carbon Design Systems Team to Accelerate Availability of Virtual Hardware Platforms for Architecture Design and Software Development (Oct. 29, 2007)
Components generated by Carbon Model Studio plug directly into CoWare’s standards-based SystemC environment and can be distributed to software users worldwide. Carbon Model Studio’s graphical user interface enables the user to create a Carbon model, configure its software-visible registers, and link with Platform Architect’s transaction-based interfaces for reuse across multiple abstraction levels and interconnects. |
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CoWare Platform-driven ESL Design Methodology Reduces Design Cycles for IBM PowerPC 440 and IBM CoreConnect(TM)-based Applications (Sep. 24, 2007)
IBM PowerPC 440 Processor Support Package and IBM CoreConnect Bus Library Are Latest Additions to CoWare’s Fast-Growing, SystemC-based Model Library |
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CoWare Collaborates with STMicroelectronics to Create an Advanced ESL Design Automation Environment for ST's Next Generation Custom Processors (Sep. 17, 2007)
CoWare announced it has collaborated successfully with STMicroelectronics to create an advanced ESL design automation environment based on CoWare's Processor Designer and CORXpert(TM) Personalization Kit for STMicroelectronics custom processors. |
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Synopsys Announces DesignWare System-Level Library (Sep. 17, 2007)
The library provides high- performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare Cores and ARM® AMBA® interconnect components. All DesignWare System-Level Library models are written in SystemC and work in IEEE 1666 (SystemC) compliant simulation environments, making them tool- independent. |
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Accellera Approves Functional Design Verification Standard (Aug. 23, 2007)
The Accellera OVL standard includes a library of assertion checkers provided as an open standard. It improves electronic design verification when using Hardware Description Languages (HDLs) and results in better quality designs by enabling effective use of ABV methodologies. |
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HD Lab, Inc. Releases "SystemC Behavioral Synthesis Style Guide" (Jul. 23, 2007)
As compared to traditional RTL-based design methods, the SystemC design methodology described can yield significant savings in overall design cycle time anywhere from 1/3 to 1/2. The guide includes examples of design blocks in excess of 3 million gates being designed using SystemC descriptions. The guide also follows and implements JEITA SystemC working group’s proposal on behavioral synthesis guidelines. |
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Forte Announces Cynthesizer 3.3 with First SystemC to GDSII Flow; Adds SystemC Behavioral IP Library and Graphical Analysis Environment (Jun. 07, 2007)
Forte Design Systems today announced the availability of version 3.3 of its Cynthesizer™ SystemC synthesis product. Cynthesizer v3.3 is the first high-level synthesis product to offer a direct path from high-level SystemC to GDSII by integrating Cynthesizer and Magma Design Automation's Blast Create™ synthesis technology and Blast Fusion® place-and-route technology. |
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Sonics Plus Partners Equals Complete ESL Strategy (Jun. 05, 2007)
Key enhancements in SonicsStudio 4.6 include the availability of ''SystemC-only'' versions of customer configured SMART Interconnects for integration into partner ESL environments, generation of ''black box'' Sonics SystemC models for software developers, support for automated adaptation between different transaction layer modeling (TLM) abstractions, and methodology improvements to ensure cycle accuracy of Sonics' SystemC models. |
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CoWare, AXE, and BeatCraft Integrate CoWare Virtual Platform, axLinux and JAKAR Media Framework (Jun. 05, 2007)
The Integration Reinforces the Value of Virtual Platforms for Software Development and Extends CoWare's Ecosystem for the Delivery of Software-Driven Architecture Development Solutions |
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Sonics and JEDA Technologies Deliver ESL Validation (May. 25, 2007)
Sonics Inc. today announced a working partnership with JEDA Technologies to deliver validated SystemC models of Sonics SMART Interconnect solutions. |
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CriticalBlue Announces Multicore Methodology for Single Threaded Software (May. 17, 2007)
The company's programmable coprocessor methodology enables multicore platform design while eliminating the need to redevelop applications software to use multiple threads, a time-consuming task with testability and reliability challenges and difficult-to-predict performance outcomes. |
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ChipVision breakthrough ESL technology enables interactive creation of RTL code optimized for low-power consumption (May. 15, 2007)
Using this technology at the system level to analyze power can result in pre-RTL energy savings of up to 75 percent, shorten time-to-results by a factor of 60, and create code that is nine times more compact. It reduces development costs by achieving results far faster than other lower-level methods. |
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CoWare Virtual Platform Product Family Adopted by Fujitsu For Completing Their Next-Generation SoC Design Flow (May. 14, 2007)
CoWare's SystemC-based solution, comprehensive IP library, multicore support, and high-performance simulation technology will provide the framework for shortening design cycle time and optimizing Fujitsu's design flow. The solution includes CoWare Virtual Platform, CoWare Model Designer, CoWare Model Library technologies, and CoWare services, all of which will enable Fujitsu to leverage CoWare's experience and expertise in platform-driven ESL design. |
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Commentary: ANSI C won't work for ESL (May. 10, 2007)
While SystemC has been accepted by most systems, semiconductor, and EDA companies as the language of choice for high-speed system-level modeling, there is a continued debate over which language is best for electronic system level (ESL) synthesis. |
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Bluespec Adds System-Level Building Blocks to AzureIP Foundation Library (May. 07, 2007)
The new blocks include ARM AMBA AXI and AHB and Open Core Protocol (OCP)-IP interface bus component libraries comprising parameterized bus structures, bus interface transactors and data type libraries. |
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Bluespec, EVE Create Platform for ESL Verification, Modeling, Architectural Design (May. 07, 2007)
The link between Bluespec's ESL synthesis and EVE's ZeBu hardware-assisted verification platform of accelerators, emulators and field programmable gate array (FPGA) prototypes offers high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyping, modeling and verification |
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SystemC and ESL in 2007: Everyone's Talking the Same Language (Apr. 17, 2007)
The Open SystemCT Initiative (OSCI) released a new report today confirming worldwide adoption of SystemC is strong and continues to grow, and that SystemC user groups in all geographies are quickly adding members and taking an active role in promoting standardization efforts. |
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Evatronix Demonstrates Transactional Model of USBHS-OTG Controller (Apr. 16, 2007)
USBHS-OTG-TLM functionality models subset of USBHS-OTG-MPD core including advanced features such as latency buffers and USB protocol-aware multichannel DMA. The organization of the buffers, using system memory as endpoint storage location, significantly reduces the size of expensive on-chip memory and allows users to optimize memory resources management according to the needs of the system. |
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Commentary: ESL should drive emulation (Apr. 13, 2007)
Conventional wisdom says that when it comes to design, you can either have a design that simulates quickly, but is not accurate. Or, you can have one that is hardware accurate but runs far too slowly for meaningful software debug or architectural performance analysis. |
