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Axilica Offers tool for behavioral synthesis of hardware designs from UMLLondon, United Kingdom -- March 10, 2008 -- Axilica Limited demonstrates “FalconML” a state of the art product for behavioral synthesis of hardware designs from UML that targets FPGAs or ASICs. Axilica Limited demonstrates “FalconML” at DATE conference on 10th – 14th March 2008, Munich, Germany. FalconML is a powerful new tool developed by Axilica to deliver behavioural synthesis of FPGA or ASIC-directed hardware designs from UML. FalconML radically improves designer productivity, allowing electronic chip design companies to:
What is FalconML? FalconML is a front-end EDA tool that initiates the design process at the UML specification level. It enables true software/hardware partitioning and delivers an output compatible with all EDA back-end flows. The advanced behavioural synthesis engine in FalconML provides routes from UML to both SystemC (for high-performance functional simulation) and to RTL (targeting both FPGAs and ASICs). Silicon IP generated by FalconML can integrate with legacy IP through direct control of design interfaces, allowing such IP to be utilised in new high-performance large-scale VLSI solutions, while taking advantage of the accelerated design process offered by FalconML.
Axilica Limited provides products and services to support the rapid development of electronic systems. FalconML is now available for evaluation. About Axilica Ltd
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