Browse >>
New Verification IP
-
BoW Verification IP
- Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification
-
USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
-
MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
-
UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
-
TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
-
Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
-
Ethernet Preemption Verification IP
- Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
-
MIPI A-PHY Verification IP
- Supports MIPI A-PHY specification 1.0 and 1.1
- Supports single lane and dual lane, point-to-point and serial communication technology
-
Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
-
MIPI I3C Verification IP with IBI feature enabled
- Push-pull mode,
- Open drain switching,
- CCC, command
-
UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
-
Synthesizable DDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
Top Verification IP
-
1
BoW Verification IP
- Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification
-
2
Synthesizable DDR4 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
-
3
Verification IP USB 2.0
-
4
VC Verification IP for USB
-
5
USB Type-C and Power Delivery Verification IP
- Compliant with standard USB PD Rev2.0, V1.1 and TYPE‐C Rev1.1 specifications.
- Supports Consumer, Provider, Consumer/ Provider &
- Provider/Consumer testing.
-
6
DDR4 DIMM Memory Model
-
7
DDR4 Memory Model
-
8
AMBA AXI3 Verification IP
-
9
CPRI Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
-
10
MIPI DSI with D-phy Verification IP
-
11
USB 2.0 SystemVerilog Verification IP
-
12
MIPI CSI-2 with C phy Verification IP
- Compliant to MIPI CSI-2 Interface Specification version 1.1 and MIPI D-PHY version 1.1
IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Verification IP Catalog