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Top Verification IPs Over the Last Two Weeks
(Last update: May. 11)
• ATA/ATAPI-8 verification IP based on e (Specman) with optional SystemVerilog interface. Fully eRM compliant. from HDL Design House
• IEEE 1394b-2000 VERA Link Layer model from Persistent Systems Pvt. Ltd.
• DDR1/DDR2/DDR3, and MobileDDR Model from Virage Logic Corp.
• Verification IP for AMBA (AXI, APB, AHB) bus from Denali Software, Inc.
• AXI Monitor from Synopsys, Inc.
• AXI System Verilog IP from HCL Technologies
• AMBA AHB and APB Bus Monitor from Gaisler Research
• AMBA 2.0 APB Slave from Synopsys, Inc.
• USB Universal Testbench Verification IP from Cadence Design Systems
• AXI Master from Synopsys, Inc.
• AMBA 2.0 AHB Monitor from Synopsys, Inc.
• Ethernet Verification from nSys Design Systems
• Verification IP for Ethernet from Denali Software, Inc.
• AHB Master Transactor from eInfochips, Inc.
• Serial ATA Port Multiplier / Port Selector test bench from ExpertIO, Inc
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New Verification IP
• PCI Express BFM for FPGA designers from Tarek Verification Systems
(May. 05, 2008)
• ATA/ATAPI-8 verification IP based on e (Specman) with optional SystemVerilog interface from HDL Design House
(Apr. 21, 2008)
• SERDES Verification IP from Tarek Verification Systems
(Mar. 31, 2008)
• SATA 2.6 Verification IP from Tarek Verification Systems
(Jan. 28, 2008)
• MIPI DSI Verification IP from Arasan Chip Systems
(Jan. 02, 2008)
• PMBus Universal Verification Component from HDL Design House
(Dec. 13, 2007)
• HyperTransport Universal Verification Component (uVC) from HDL Design House
(Dec. 03, 2007)
• System Verilog based AXI system verification IP from HCL Technologies
(Nov. 19, 2007)
• Interlaken Bus Functional Model (BFM) and Monitor from Rockfish Technology
(Oct. 25, 2007)
• Universal Verification Component supporting two protocols AMBA APB and SPI from HDL Design House
(Oct. 18, 2007)
• AMBA AHB and APB Bus Monitor from Gaisler Research
(Aug. 30, 2007)
• I2C SystemVerilog Verification Component from HDL Design House
(Aug. 30, 2007)
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