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Synopsys' DesignWare Verification IP Enhanced to Support New SATA 6Gbps Specification (Jun. 18, 2008)
The DesignWare Verification IP supports all major simulators and verification languages including Verilog, SystemVerilog, VHDL and Vera, allowing designers to quickly and efficiently create a comprehensive SATA- based environment. In addition, the Verification IP for SATA delivers up to 5X performance improvement when used with Synopsys' VCS® simulation tool |
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eInfochips announces AVM 3.0 & OVM Compliant SystemVerilog AMBA AHB Verification IP (Jun. 13, 2008)
Integration of AMBA AHB AVM 3.0 Ensures Availability of OVM Compliant High-Quality Verification IP for Advanced SystemVerilog Verification |
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Cadence Delivers OVM-Compliant Verification IP (Jun. 09, 2008)
Cadence today announced the availability of the first two advanced testbench verification IP (VIP) products that are compliant with the Open Verification Methodology (OVM) |
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Denali Software Announces Availability of MMAV 2008 Verification IP (May. 22, 2008)
This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols. |
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Arasan Chip Systems Introduces New Low Voltage SDIO Validation Platform (Apr. 16, 2008)
The new SD/SDIO Device HVP is a SD host platform tool based upon Arasan's SD/SDIO host controller used for SDIO device validation. Fully compliant with SD/SDIO v2.0, SD Memory v2.0, and MMC v4.3, the SD socket can interface to any standard SD or MMC card for fast validation. |
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nSys Offers World's Largest Portfolio of Verification IPs for OVM-Based SystemVerilog Environments (Feb. 19, 2008)
nSys announced today the availability of Verification IP products integrated with the Open Verification Methodology (OVM) environment. The nSys Verification IPs for OVM-based environments are available for standard interfaces such as AMBA AXI, Ethernet, PCIe, SATA, and USB etc |
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SoCVerify Kit by HDL Design House - HDL Design House announces its Verification IP (VIP) library (Feb. 19, 2008)
SoCVerify Kit covers a large number of standards and protocols such as I2C, HyperTransport, Serial Rapid IO, SATA, SAS, LPC, PCI, PCI-X, SPI4, SMBUS, PMBUS and each VIP constituting SoCVerify Kit library supports a wide set of verification methodologies such as: eRM, UVC, OVM. |
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Rockfish Technology Launches Interlaken Verification IP (Oct. 22, 2007)
The Interlaken BFM has an easy to use interface for the customer’s testbench consisting of a clocked data bus and control lines. Alternatively, Rockfish Technology offers a SystemVerilog packet based testbench for those customers needing a complete solution. |
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Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM) (Oct. 19, 2007)
The IEEE 1394 Function Controller uVC verifies designs that include IEEE 1394 Function Controller. This uVC consists of a complete set of elements for stimulating, checking, and collecting coverage information for the IEEE 1394 protocol, as well as thoroughly exercises the link controller. |
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VinChip Announces Verification Testbench for Certified Wireless USB (Aug. 07, 2007)
The testbench includes a configurable functional model for Wireless USB Host, Device and WiMedia MAC. Certified Wireless USB testbench is purely Verilog based which assures our customer's Wireless USB core to be in line with the specifications. |
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OCP-IP Announces Support for Cadence's Assertion Based OCP Protocol Verification IP (Jul. 09, 2007)
OCP-IP today announced their support of Cadence’s Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. OCP’s ascendance as the system architecture “backbone” within increasingly complex consumer and portable designs has driven the need for improved verification at the block, chip and system levels. |
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ARM Unleashes Adaptive Verification IP For On-Chip Communication (Jun. 04, 2007)
Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue. |
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Avery Design Systems Announces Support for PCI Express IO Virtualization and AMBA AXI (May. 24, 2007)
PCI-Xactor support for the PCI Express IO Virtualization (IOV) and Address Translation Services (ATS) standards based on Single Root IOV (SR-IOV) will be available in June 2007 and Multi-Root IOV (MR-IOV) support is planned for H2'07 release. The solution is comprised of enhanced Root Complex, Endpoint, and Switch BFMs, protocol assertions, and a compliance test suite. |
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Silicon Interfaces announces the release of its new RapidIO Physical Layer Interface OpenVera Verification IP (May. 09, 2007)
Silicon Interfaces' RapidIO Physical Layer Interface OpenVera Verification IP is a fully documented, off the shelf component for the verification of the RapidIO Physical Layer Interface Controller. RapidIO is a Packet-switched Interconnect primarily intended for an Intra-system Interface for chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels. |
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Denali Launches New Product to Speed System-On-Chip Verification (Apr. 16, 2007)
Denali Software today announced the availability of PureSpec(TM) SystemRDL, a verification IP (VIP) product that automates functional verification of configuration registers for system-on-chip (SoC) designs. |
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OCP-IP Standardizes on Synopsys' DesignWare Verification IP for OCP-IP's CoreCreator Verification Toolset (Apr. 10, 2007)
Synopsys and OCP-IP today announced that they are collaborating to provide Synopsys' DesignWare(R) Verification IP (VIP) as part of OCP-IP's CoreCreator verification toolset. |
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TEMENTO SYSTEMS announces the introduction of a Bus Trace Analyzer for On-Chip AMBA and ARM processor-based Verification (Apr. 10, 2007)
Temento Systems has launched a new line of instrumentation IP specifically focussed on the debugging of embedded systems with the introduction of a Bus Trace Analyzer for AMBA and ARM processor-based SoC's |
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VinChip Systems announces USB PHY Verification Services (Apr. 09, 2007)
Home grown or third party USB PHY (UTMI/UTMI+/ULPI) can be tested with VinChip Verification IP containing silicon proven VinChip RTL and test environment to identify bugs early in the design . Customers can get full access to VinChip RTL and full test case database as a part of this service. Post silicon customer's PHY will be tested in VinChip FPGA emulation environment and checked for USB – IF compliance |
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Avery Design Delivers PCI Express Gen2 Verification IP and Compliance Test Suite (Mar. 13, 2007)
PCI-Xactor for PCI Express is one of the most widely used and proven solutions for functional verification of PCI Express designs. The new release fully supports Gen2 including Root Complex, Endpoint, and Switch models, protocol assertions, and compliance tests. Core-level compliance has been enhanced through an innovative application port driver methodology (DUT integration) to maximize controllability and observability. |
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eInfochips Supports the Mentor Graphics' Questa(TM) Vanguard Program for AMBA AHB SystemVerilog Verification Component (Dec. 18, 2006)
Through the Questa Vanguard program, eInfochips will provide verification IP options to help build an established, comprehensive SystemVerilog community for the Questa advanced verification platform user |
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YOGITECH Introduces Industry First OCP Universal Verification Component (Oct. 02, 2006)
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Synopsys Releases Verification IP for the OCP Interface (Sep. 13, 2006)
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IPextreme and NXP Semiconductors Bring First FlexRay Verification Environment to Market; New e Verification Component Improves Quality and Predictability for FlexRay Protocol Designers (Sep. 12, 2006)
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Cadence Introduces Universal Verification Components; First Verification-Plan-Enabled Verification IP Integrates Compliance Management and Mixed Language Support (Aug. 07, 2006)
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Cadence and ARM Deliver Innovative Kit to Speed Verification Closure for ARM Processor-Based Designs (Jun. 26, 2006)
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Knowlent Ensures Analog Sign-Off With Latest Opal Verification Platform; New 4.0 Release Offers Testbench for Up-coming PCI Express Gen 2 Standard (Jun. 19, 2006)
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YOGITECH Extends OCP Verification Component Functionality (Jun. 13, 2006)
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nSys leads the way to announce PCI Express Gen2 VIP availability in SystemVerilog (Jun. 12, 2006)
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NextIO and Denali Team to Enable First I/O Virtualization Designs for PCI Express (Jun. 09, 2006)
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IntelliProp Releases Additional Verification IP for Storage Interfaces (May. 30, 2006)
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