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The development of verification environments for today's system-on-a-chip (SoC) designs is becoming more and more complex. With increasing design complexity, large number of in-house and third-parties IPs, different protocols being used in the design, and limited resources design verification represents a bottleneck in product development process. Ultimate requirement is to have support and solutions from reliable verification solutions providers.

This corner will bring to your attention the latest News, latest products, latest initiative in this field.

Featured Products:

SATA I SVC, Serial ATA (SATA) System Verification Component from ExpertIO, Inc
SATA II SVC, Serial ATA II System Verification Component from ExpertIO, Inc
FC SVC, Fibre Channel Verification Component from ExpertIO, Inc
SAS SVC, Serial SCSI (SAS) System Verification IP from ExpertIO, Inc
SATA PM/PS SVC, Serial ATA Port Multiplier / Port Selector test bench from ExpertIO, Inc
pcimaster_fx, PCI / PCI-X Master from Synopsys, Inc.
usbhost_fz, Universal Serial Bus 2.0 Host from Synopsys, Inc.
enethub_fx, IEEE 802.3 Hub from Synopsys, Inc.
sio_txrx_vmt, Serial I/O TxRx from Synopsys, Inc.
DWMM, DesignWare Memory Models from Synopsys, Inc.

   
Latest News:
  • Arasan Chip Systems Introduces New Low Voltage SDIO Validation Platform (Apr. 16, 2008)
  • nSys Offers World's Largest Portfolio of Verification IPs for OVM-Based SystemVerilog Environments (Feb. 19, 2008)
  • SoCVerify Kit by HDL Design House - HDL Design House announces its Verification IP (VIP) library (Feb. 19, 2008)
  • Rockfish Technology Launches Interlaken Verification IP (Oct. 22, 2007)
  • Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM) (Oct. 19, 2007)
  • Industry Articles :
  • Verification of IP Core Based SoC's (Apr. 14, 2008)
  • Verification IP Reuse For Complex Networking Asics (Apr. 02, 2008)
  • To develop or buy a Verification IP (Jan. 17, 2008)
  • OCP VIP: A cost effective and robust qualification process for multimedia and telecom SoC designs (Jan. 09, 2008)
  • Development of Verification Environment for Layered Protocol using SystemVerilog (Jul. 02, 2007)