PCIe 2.0 for ASIC - RTL-level IP controller that supports PCIe root port, endpoint, switch-up, switch-down, and bridge IP Core | PLDA Semiconductor IP Listing

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PCIe 2.0 for ASIC - PCIe 2.0 for ASIC - RTL-level IP controller that supports PCIe root port, endpoint, switch-up, switch-down, and bridge

PLDA
PLDA, the world's largest PCI IP Core vendor (Gartner, 2007), designs and sells a wide range of ASIC and FPGA interfacing solutions for the PCI and derivative markets (PCI Express, PCI-X, CompactPCI, and PC104/PC104+). The company offers complete solutions to a global market, including IP cores, hardware (prototyping boards that include a reference design and IP controller), software, consulting services, and comprehensive technical support provided directly by the IP designers.

Founded in 1996, PLDA has offices in San Jose, CA and Aix-en-Provence, France. Its worldwide distribution and partnership network include Altera, Altima, Arrow, Eastronics, EBV and Paltek.

13 Product(s) Listed

Part Number Product Description

USB3.0_developmentkit SuperSpeed USB (USB 3.0) Development Kit

USB3.0_Device_IP SuperSpeed USB (USB 3.0) Device IP

USB3.0_HostIP SuperSpeed USB (USB 3.0) Host IP

PCIe 2.0 for ASIC PCIe 2.0 for ASIC - RTL-level IP controller that supports PCIe root port, endpoint, switch-up, switch-down, and bridge

PLDA AHB-PCIe Bridge AHB-PCI Express Bridge IP Core

PLDA PCIe XpressRich: ASIC RTL-level IP controller (Verilog and VHDL) that supports all PCIe 1.1 & 2.0 configurations (root port, endpoint, switch-up, switch-down, and bridge)

PLDA AXI-PCIe Bridge The AXI-PCI Express Bridge IP Core creates a bridge between an AXI bus and a PCIe bus

PLDA EZ DMA DMA controller designed for the Xilinx Virtex 5LXT built-in PCIe interface. x1 x4 and x8 lanes supported

PLDA AHB-PCI Bridge AHB-PCI Bridge

PCIe XpressRich: FPGA RTL-level IP controller (Verilog and VHDL) that supports all PCIe configurations (root port, endpoint, switch-up, switch-down, and bridge)

PCIe XpressLite: FPGA RTL-level IP controller (Verilog and VHDL), for FPGA designs, that offers the strengths of the PCIe technology while hiding the complexity of the protocol

PLDA PCI-X 32/64-MT PCI-X Master/Target IP Core - 32/64-bit ~ 133MHz

PLDA PCI32/64-MT PCI Master / Target IP Core Core - 32/64bit 33/66MHz

Corporate Headquarters
PLDA
Parc Club du Golf - Bât 11-Rue Guillibert
13856 Aix-en-Provence
France

PLDA, Inc.
2570 North First St. 2nd floor
San Jose, CA - 95131-1036
USA

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