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Synopsys Broadens DesignWare SATA Solution With Device IP (Jul. 14, 2008)
Comprehensive SATA IP Portfolio Including Device, Host, PHY and Verification IP Passes Interoperability Testing, Reducing Integration Risk for SoC Designs |
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Silicon Image Offers Mobile Phone Manufacturers a Better Way to Implement an HDTV Connection (Jul. 14, 2008)
Silicon Image today announced its ultra-low-power interface solution consisting of a VastLane(TM) SiI9206 HDMI(TM) transmitter PHY semiconductor and a companion link layer IP core for use in consumer mobile device applications. |
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ARM Mali-200 GPU World's First To Achieve Khronos OpenGL ES 2.0 Conformance At 1080p HDTV Resolution (Jul. 14, 2008)
The ARM® Mali™-200 graphics processing unit is the first GPU on today’s market to pass Khronos conformance testing at up to 1080p HDTV resolutions. |
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Virage Logic Expands Memory Interface Product Portfolio With New DDR3 Solution That Supports Speeds Up to 1.6 Gb/s (Jul. 14, 2008)
Comprising a DRAM memory controller, digital PHY, DLL, and I/O, Intelli DDR3 provides a true System Aware IP(TM) solution that is able to mitigate and manage the high-speed interconnect effects that must be addressed at the package as well as board level. |
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A New Era for Dolphin Integration's Embedded Memories (Jul. 14, 2008)
Dolphin Integration is announcing a blockbuster sRAM Trio for embedding in circuits at 130 nm in G process and at 90 nm in LP process. |
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Chips&Media unveils Boda7503, High-Definition video IP solution including AVS (Jul. 11, 2008)
Chips&Media’s Boda7503 is a highly optimized decode core supports H.264, MPEG-2, MPEG-4, VC-1, RealVideo, MJPEG in addition to AVS up to HD(1080p). |
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Cambridge Consultants XAP5 core sets new standard for 16-bit processors (Jul. 10, 2008)
XAP5 combines the economy of a 16-bit data word with a 24-bit address space for large programs up to 16 Mbytes, which suits devices designed for data-centric communications applications in markets such as consumer, industrial and retail.
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Dolphin Integration announce a breakthrough in silicon IP for power management (Jul. 07, 2008)
SRO and SRI Switching Regulators innovate with their inductorless architecture, a technique used for the first time in silicon IP. |
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Evatronix adds 6502 and 80186XL ISA-compliant IP cores to its portfolio (Jul. 07, 2008)
Both solutions add up to Evatronix obsolete part replacement IP core family. |
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Sonics Eliminates Barriers to Multichannel Memory Management Industry Adoption With New Interleaved Multichannel Technology(TM) (Jul. 01, 2008)
IMT utilizes an innovative memory interleaving methodology as a foundation for managing up to 8 external DRAM channels. User-controlled interleaving addresses the key challenge of adopting multichannel architectures: ensuring that the memory traffic is divided evenly among the channels. |
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New SonicsSX SMART Interconnect Solution Solves Memory Performance Problem for High Quality, High Definition Video SoCs (Jul. 01, 2008)
Designed for SoCs requiring high quality, high definition, or HQHD, video support, SonicsSX accelerates video performance and eases global integration of intellectual property cores and subsystems onto a single chip. |
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MoSys Demonstrates Blu-Ray Solution for Home Entertainment Applications (Jul. 01, 2008)
The MoSys solution is the first in the industry to support all next-generation Blue-Laser and current Red-Laser DVD formats in a single, integrated design for multi-format DVD players and recorders, game consoles, PCs, advanced Set-Top boxes, and digital video recorders. |
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Lattice Enhances its Wireless Base Station Solutions Portfolio (Jun. 23, 2008)
Lattice Semiconductor Corporation today announced the availability of three new Intellectual Property (IP) core and reference design products targeting the wireless communications market. |
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Kaben Wireless Silicon releases high-performance frequency synthesizer for WiMAX applications (Jun. 17, 2008)
The Fractional-N synthesizer delivers a -116 dBc/Hz phase noise performance and -90 dBc spurious response at 6 GHz output |
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IP Cores, Inc. Shipped Ultracompact AES and AES/GCM IP Cores for Actel FPGA Supporting FIPS-197, IEEE 802.1AE MACsec and P1619.1 Standards (Jun. 16, 2008)
Starting at 800 tiles for AES1-8E and delivering 11.2 Mbps on RTSX radiation-tolerant devices, AES and AES/GCM cores provide a compact and high-performance solution for an FPGA designer working on a secure communication solution. |
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Virage Logic Unveils One Mega-Bit Embedded Reprogrammable Non-Volatile Memory (NVM) on Standard CMOS Process (Jun. 16, 2008)
Combining user-defined functionality with Virage Logic’s high-capacity read-only memory (ROM) and NOVeA® Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up to 16 Megabits of code storage and is manufactured on industry standard CMOS processes with no additional mask or process steps. |
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Radiocomp & Altera partner on OBSAI/CPRI cores (Jun. 12, 2008)
Denmark-based Radiocomp and Altera Corporation today announced an integrated, rapid development solution for developers of WiMAX and 3GPP LTE base station equipment. |
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Faraday Announces the First Commercially Available 1GHz Memory Compiler to Enable GHz CPU & SoC Designs in UMC 90nm (Jun. 12, 2008)
The single-port memory compiler utilizes advanced layout and circuit design techniques to provide up to 1GHz speed and keeps the same power and area requirement as generic memory solutions. |
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austriamicrosystems further expands field-programmable OTP memory portfolio for its advanced 0.35um process family (Jun. 12, 2008)
The polyfuse-based OTP memory cell “PPROM” is available in two fixed sizes of 4x8 bit and 16x8 bit and comes with a parallel interface. It is accessible like a static RAM and offers direct addressed outputs. The “PPTRIM” blocks available in sizes of 8 bit, 16 bit, 32 bit, 48 bit and 64 bit offers a three wire interface and auto-load at poweron reset. |
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Synopsys Announces DesignWare IP for PCI Express with PCI-SIG I/O Virtualization Technology (Jun. 11, 2008)
The PCI-SIG I/O Virtualization (IOV) technology, which builds on the PCI Express (PCIe) protocol stack, reduces the system hardware requirements by enabling the simultaneous sharing of peripherals across multiple CPUs or operating systems. |
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Tiempo announces a fully-asynchronous delay insensitive DES crypto-processor chip (Jun. 11, 2008)
Tiempo released a clock-less crypto-processor chip - DES4- including four different DES cores available as IP and able to execute standard ciphering algorithms DES, DES-1, 3DES & 3DES-1. |
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GDA Demonstrates its PCI-Express Gen 2 Controller (GPEX-GEN2) at 5Gbps for High Performance Applications (Jun. 11, 2008)
GDA Technologies today announced successful functional operation of its Gen2 PCI Express Controller on its hardware platform. |
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Lattice Expands Wireless Solutions with 3GPP-LTE CTC Decoder IP Core (Jun. 09, 2008)
TurboConcept Optimizes its 3GPP-LTE Turbo Decoder IP Core for LatticeSC/M and LatticeECP2/M FPGA Devices |
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IPextreme® Brings ColdFire® Architecture to the FPGA Masses (Jun. 09, 2008)
IPextreme today announced an FPGA-optimized soft version of Freescale’s V1 ColdFire® core available free of charge to Altera’s Cyclone III FPGA customers |
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Freescale and Altera Partner to Deliver World's First Soft ColdFire(R) Cores on FPGAs (Jun. 09, 2008)
Popular V1 Core Available at No Charge Through IPextreme for Altera's Cyclone(R) III FPGA; SOPC Builder-Ready Component Backed by Broad Ecosystem |
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Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm (Jun. 09, 2008)
Direct connection to the battery (e.g. Li-Ion) for some logic islets of SoCs requires dealing with “high voltage”, up to 3.6 V, while for others ultra low leakage is needed far below the performances offered by products available on the market. |
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Noesis Technologies releases 10Gbps AWGN channel emulator IP (Jun. 06, 2008)
The core is fully programmable, able to support throughput rates up to 10Gbps, rendering it an ideal solution for channel emulation of high data rate applications such as GPON, G.975 and others. |
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Innovaide Releases Licensable Packet Processing and Traffic Management IP (Jun. 05, 2008)
Innovaide is First-to-Market with licensable Carrier Grade designs for Classification, Forwarding and Traffic Management. The Verilog blocks scale from 5Gig to 40Gig performance in FPGA/ASIC implementations. |
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Arasan Chip Systems PCI Express Gen2 Solution Named to PCI-SIG Integrators List (Jun. 05, 2008)
New Flexible PCIe IP Core and Development Platform Passes Rigorous Interoperability and Compliance Testing |
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Evatronix enhances its Ethernet MAC product line with MAC-1G PCS IP core (Jun. 05, 2008)
Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations. |
