ESL Design News
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Imperas Releases Fast Models of PowerPC Processors Through Open Virtual Platforms (OVP) Initiative (Tuesday Jun. 08, 2010)
Imperas today announced the release of fast models of PowerPC processors. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching over one thousand million instructions per second (MIPS).
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Calypto's Industry Expands Lead in ESL Verification with Latest SLEC Release (Monday Jun. 07, 2010)
Calypto® Design Systems, Inc. (www.calypto.com) today announced that its latest SLEC® 5.0, release includes breakthrough technology for verifying deep, complex loop structures in ESL flows. SLEC is the industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations.
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Imperas and Open Virtual Platforms (OVP) Initiative Release Full Support for MIPS Technologies' MIPS32 M14K Processors (Thursday Apr. 01, 2010)
Imperas today released models of the new MIPS32® M14K™ and M14Kc™ processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools.
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Denali Software and Carbon Team for Transaction-Level Model Distribution (Wednesday Mar. 24, 2010)
Denali and Carbon Design Systems today announced a collaboration to provide designers with cycle-accurate models of Denali's configurable Databahn(TM) DDR SDRAM controller IP for virtual platforms.
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Open Virtual Platforms (OVP) Releases Vendor-Verified High Performance Models of Virage Logic's ARC Processors (Tuesday Mar. 23, 2010)
The OVP initiative has announced the release of models of Virage Logic’s ARC processor cores. Models of the Virage Logic ARC® 600 and ARC® 700 families of processor cores have been released, including the ARC® 605. Additionally, Virage Logic and Imperas have cooperated on the verification of the functionality of the models.
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CoWare Announces Software Development Solution for ARM Cortex-A5 and ARM Cortex-M4 Processor-Based Designs (Wednesday Mar. 17, 2010)
CoWare today announced support for Fast Models from ARM for Cortex™-A5 and Cortex-M4 processor IP in CoWare’s SystemC-based software development solution. Customers around the world have already successfully deployed CoWare virtual platforms using Fast Models from ARM.
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Carbon Unveils New Generation of ARM Models with Availability of Mali Models (Monday Mar. 08, 2010)
Carbon Design Systems announced today immediate availability of virtual models for ARM® Mali™ Graphic Processor Units (GPUs). These new models, including the Mali-200 and Mali-400MP, are compiled directly from the ARM register transfer level (RTL) code and are 100% implementation accurate.
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CoWare and Tensilica Deliver Software Development Solution for Multi-Core Tensilica-Based Platforms (Wednesday Dec. 16, 2009)
New Software Releases From CoWare and Tensilica Support Advanced Software Development Capabilities of The CoWare Platform Architect and Virtual Platform Technology
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Carbon Further Expands ARM IP Library (Thursday Dec. 10, 2009)
Carbon Design Systems today announced immediate availability of a comprehensive array of implementation-accurate models of ARM® intellectual property (IP) cores.
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CoWare and ARM Partner to Enable Rapid Configuration of AMBA NIC-301 Network Interconnect-based SoC Designs in SystemC (Wednesday Oct. 21, 2009)
CoWare and ARM today announced their partnership to provide system designers with a new SystemC solution for the efficient configuration of AMBA® NIC-301 Network Interconnect based SoC Designs.
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Carbon Adds Support for Fast Models from ARM (Wednesday Oct. 21, 2009)
Carbon today announced full support for Fast Models from ARM® in its SoC Designer™ virtual platform. This support will enable users to leverage a single virtual platform environment for every aspect of their development process. SoC Designer now enables users to easily perform tasks ranging from application software development to low-level firmware development and even architectural design.
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Carbon Automates AXI Interconnect Model Creation (Thursday Oct. 01, 2009)
Carbon Design Systems today announced availability of Carbon Model Studio for AMBA™ Designer from ARM®, software for the creation of implementation-accurate models of AMBA interconnect fabric.
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Carbon Design Systems Adds Co-Simulation Model Library to Expanding System-Level Validation Tool Suite (Tuesday Sep. 08, 2009)
arbon Design Systems today announced immediate availability of the Carbon Model Library for co-simulation that includes the most advanced ARM processors.
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Siemens Adopts CoWare Electronic System Virtualization Solutions For the Development of Industrial Ethernet Components (Monday Aug. 17, 2009)
Using CoWare Platform Architect and CoWare Virtual Platform, Siemens developed a virtualized model of a PROFINET device. The analysis visibility and debugging control of the virtualized model delivers a more efficient and productive environment over traditional methods for architecture design and software development.
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Virtutech Announces Simics Full-System Checkpointing for SystemC Based Transaction-Level Modeling (Monday Jul. 27, 2009)
Virtutech today announced that Virtutech’s Simics® platform now provides full-system checkpointing for SystemC™ based transaction-level modeling (TLM).
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Cadence Introduces First TLM-Driven Design and Verification Solution to Increase Engineering Productivity over RTL-based Flows (Thursday Jul. 16, 2009)
The Cadence® solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive® Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto® sequential logic equivalence checking, the first version of the TLM-driven design and verification methodology, and customer adoption services.
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CoWare Reduces Design Cost for Complex ARM AMBA Platform Optimization (Monday Jun. 15, 2009)
CoWare announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM® AMBA®-based virtual platforms.
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Cadence and Virtutech Extend Metric-Driven Verification to Virtual Systems Development (Tuesday May. 19, 2009)
Cadence and Virtutech today announced a collaboration to integrate Cadence® Incisive® Software Extensions with the Virtutech Simics® high-speed system-level virtual platform.
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CoWare and Carbon Announce CoWare Model Library Availability of Implementation-Accurate Models of ARM IP (Monday Apr. 27, 2009)
CoWare and Carbon Design Systems announced today a strategic partnership to deliver implementation-accurate models of ARM® IP targeted for CoWare’s SystemC-based design solutions. The models and model kits will include implementation-accurate solutions for the ARM Cortex™-A9 processor, AMBA®3 Interconnect (PL301) matrix, and more.
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OCP-IP Delivers New Advanced SystemC TLM Kit (Tuesday Apr. 21, 2009)
OCP-IP today announced the availability of the SystemC TLM kit for OCP. The new kit represents the first, and most advanced TLM-2.0 based, industry-ready kit in existence today.
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DOCEA Power unveils first ESL solution for modelling, simulating and optimizing the power and heat dissipation of electronic systems (Monday Apr. 20, 2009)
DOCEA Power today announced ACEplorer®, the first ESL software tool that allows designers to model, simulate and optimize the dynamic power and thermal behaviour of whole complex systems, either on-chip, on-board or with multiple boards.
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Renesas & CoWare Collaborate to Accelerate the Deployment of SH-based Virtual Platforms in Mobile, Automotive and Digital Imaging Applications (Monday Apr. 20, 2009)
CoWare, announced today a collaboration with Renesas Technology Corp. aimed at delivering better development tools to Renesas’ SH core-based software development community using virtual platforms.
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Carbon and MIPS Technologies Partner for Model Distribution (Wednesday Apr. 08, 2009)
Carbon and MIPS announced today that they have partnered to deliver models of MIPS® processor cores to Carbon’s SoC Designer customers. Development teams will now have the capability to debug their MIPS firmware code in the industry’s fastest cycle-accurate virtual prototyping environment.
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CoWare Releases Reference Library to Accelerate the Design of Long Term Evolution (LTE) Wireless Systems (Wednesday Apr. 01, 2009)
The new library adds to CoWare’s already available suite of solutions that address the challenges of designing software, algorithms and architectures for LTE networks, basestations, handsets and chip sets. The CoWare LTE Library (Compliant to 3GPP LTE Release V8.5.0) runs on the ultra-fast CoWare Signal Processing Designer multi-threaded simulator.
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CoWare Releases New Platform-Centric Software Analysis Tool to Increase Multicore Software Development Productivity (Monday Mar. 30, 2009)
The platform-centric software analysis tool is an Eclipse-based framework that provides the visibility to debug and optimize across the boundaries of processes, operating systems, cores, and hardware. It supports the configuration, acquisition and display of the acquired data. It can be made OS aware (Linux example provided) and is customizable to adapt to customer-specific analysis needs.
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Agilent Technologies' New System-Level Communications Design Software Speeds Development Cycle (Monday Mar. 09, 2009)
Agilent today announced the availability of a new platform for electronic system-level (ESL) design. The new platform delivers modeling, design-flow improvements and baseband IP libraries that can cut months from physical layer (PHY) design time for high-performance communications algorithms and system architectures in both wireless and aerospace/defense applications.
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CircuitSutra partners with GreenSocs to provide high quality SystemC based SoC modelling services (Monday Feb. 16, 2009)
CircuitSutra Technologies Pvt Ltd today announced it has entered into a partnership with GreenSocs Ltd, UK to deliver high quality SystemC based SoC modelling services to the semiconductor industry.
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OVP Simulator Smashes SystemC TLM-2.0 Performance Barrier (Friday Feb. 13, 2009)
Open Virtual Platforms (OVP) today released new native SystemC transaction level modeling (TLM)-2.0 technology to use with OVP CPU models that run to the speed of one billion (1B) instructions per second (1,000 MIPS).
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CoWare and Rambus Announce Unique ESL Architecture Design Environment for Rambus' XDR Memory Architecture (Monday Feb. 09, 2009)
CoWare and Rambus announced they have collaborated on a comprehensive ESL design environment with CoWare Platform Architect for Rambus’ award-winning XDR™ memory architecture. CoWare will distribute a SystemC model with the flexibility to match configurations of Rambus’ XDR memory subsystems.
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Mentor Graphics Announces Scalable TLM-2.0 Design Flow Using Vista and Catapult C Synthesis Electronic System Level (ESL) Design Tools (Tuesday Jan. 20, 2009)
Mentor Graphics today announced a new Scalable Design Methodology based on a layered transaction level model (TLM) that allows a single model to be taken from design concept to implementation.