Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore


Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM)


Related News

Related

Silicon Interfaces Hot IPs

Breaking News

Most Popular (Updated Daily)

October 19, 2007 -- Silicon Interfaces' IEEE 1394-1995/2000 Link Layer Controller uVC is a fully documented, off the shelf component using Cadence Incisive Plan-to-Closure Universal Reuse Methodology (URM) for functional verification environment. The URM Compliant uVC is based on an eRM compliant eVC which has been proven in the market. By Q1 2008, this uVC shall be available in OVM (Open SystemVerilog Verification methodology).

The IEEE 1394 -1995/2000 link layer controller (from now on referred to only as 1394) provides connectionless acknowledged data transfer services between a source node and destination node where node is an addressable device attached to the serial bus with at least a minimum set of control registers.

The IEEE 1394 Function Controller uVC verifies designs that include IEEE 1394 Function Controller. This uVC consists of a complete set of elements for stimulating, checking, and collecting coverage information for the IEEE 1394 protocol, as well as thoroughly exercises the link controller.

The uVC supports IEEE 1394 PHY specification at the Physical side and Transaction Layer specification at the Host side. Data transmission can be configured to be at 100, 200 or 400 Mbps and can also be configured to be asynchronous or isochronous transaction.


   

Contact Silicon Interfaces

Fill out this form for contacting a Silicon Interfaces representative.

Your Name:
Your E-mail address:
Your Company address:
Your Phone Number:
Write your message:
   

 



E-mail This Article Printer-Friendly Page