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nSys leads the way to announce PCI Express Gen2 VIP availability in SystemVerilog
Newark, CA -- June 12, 2006 -- nSys Design Systems, provider of world’s largest portfolio of Verification IPs, today announced the availability of nSys Verification Suite (nVS) for PCI Express® Gen2 in System Verilog. nSys is the only company in the world offering nVS for PCI Express Gen2 in SystemVerilog, Verilog and VHDL. The nVS for PCI Express Gen2 is the next generation VIP that builds upon nVS for PCI Express, one of the most widely accepted and proven solutions for functional verification of PCI Express designs. The nVS for PCI Express Gen2 helps find bugs before the design is implemented in silicon and is a key component of the verification environment for PCI Express Gen2 based designs. The nVS for PCI Express Gen2 accelerates the adoption of PCI Express Gen2 standard. The PCI Express Gen2 is an evolving standard that improves the link speed to 5 Gbps and enhances power saving. Atul Bhatia, Director, nSys Design Systems, says, “We realized that the developers working on PCI Express Gen2 based projects were facing a huge roadblock without the availability of any Verification IP for PCI Express Gen2 in SystemVerilog.” He further says, “As a market leader in Verilog and VHDL based Verification IPs, release of nVS for PCI Express Gen2 in SystemVerilog, Verilog & VHDL is a natural progression of our strategy to stay ahead and be a technology leader for Verification IPs”. nVS for PCI Express Gen2 features:
Availability The nVS for PCI Express Gen2 is available immediately. The nVS Verification Suites ship with full documentation and example configurations for SoC verification environments. nSys also offers services for migration to SystemVerilog and Independent verification services to its customers. About nSys nSys is the leading provider of Verilog based Verification IPs. nSys offers the world’s largest portfolio of VIPs to its customers. nSys provides products and services to Accelerate Designs of its customers, by focusing on the verification phase of ASIC/FPGA/IP development. By leveraging its vast experience in standards-based product development, the nSys team creates verification solutions that solve the most challenging functional verification problems in the world. nSys solutions are in the form of Verification IPs backed by services. For more information, please visit nSys at www.nsysinc.com or contact nSys directly at: 510-892-2951
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