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"IP Design / Physical Design" Session

Moderated by Paolo Pezzati, Cadence
Dec. 6, 2006 - 17:00-18:30
  • "Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core" by Cyril Prasanna Raj P from MS Ramaiah School of Advanced Studies

  • "Integrating PCI Express IP in a SoC" by Ilya Granovsky & Elchanan Perlin from IBM

  • "BACK-END TOOL FLOW FOR COARSE GRAIN RECONFIGURABLE IP BLOCK RAA" by Tapio Ristimaki, Claudio Brunelli & Jari Nurmi from Tampere University Of Technology

  • "Top Down SoC Floor planning with ReUse" by Fuad Abu Nofal & Monica Nofal from ChipEDA

  • "MpNoC Design: Modeling and Simulation" by Simon DUQUENNOY, Sébastien LE BEUX, Philippe MARQUET, Samy MEFTALI & Jean-Luc DEKEYSER from INRIA Futurs, Lille Best IP Prize Candidate

  • "Realizing the Performance Potential of a PCI Express IP" by K Yogendhar, Vidhya Thyagarajan & Sriram Swaminathan from Rambus Chip Technologies (Pvt) Ltd.