Design Reuse Feedback | D&R Products | Site Map | Register | MyD&R
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Multimedia IP Journal Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore
Home/Introduction
Program Committee
Exhibition
Conference Program
Pratical Information
Training & Tutorials

" IP Based Architecture" Session

Moderated by Kunihiro Asada, University of Tokyo
Dec. 6, 2006 - 11:00-12:30
  • "An Implementation Study on Fault Tolerant LEON-3 Processor System" by Zoran Stamenkovic, Christoph Wolf & Gunter Schoof from IHP GmbH & Jiri Gaisler from Gaisler Research

  • "A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect" by Mohammad Urfianto, Tsuyoshi Isshiki, Arif Khan, Dongju Li & Hiroaki Kunieda from Tokyo Institute of Technology Best IP Prize Candidate

  • "DFCI: An Efficient Scalable System-on-chip Communication Architecture" by Nan Wang & Magdy A. Bayoumi from University of Louisiana at Lafayette

  • "RAID6 accelerator in a PowerPC IOP SOC" by Gerard BOUDON, Haluk Aytac & John Fakiris from AMCC

  • "High-resolution CMOS Rotary Encoder SoC Using Magnetic Sensor Array and Statistical Angle Calculation Circuit" by Kazuhiro Nakano & Shoji Kawahito from Shizuoka Univ. & Toru Takahashi & Yoshitaka Nagano from NTN Corp. Best IP Prize Candidate