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DAY 1: December 6, 2006

AUDITORIUM			ROOM 1				ROOM 2
Time	Panel		Session	Time	Paper		Session	Time	Paper
7:00	Registration			7:00	Registration			7:00	Registration
8:15	Welcome
8:30	"Investment opportunities in IP" by Jacques Benkoski, US Venture Partners
9:00	"The role of virtual fabless providers for a predictable road to product" by Massimo Vanzi, CEO, Accent
9:30	"Hardware Initiatives in the Open Source community" by Fadi Azhari, Marketing Director, Sun Microsystems
10:00	"SoC/IP Market Overview and Outlook" Jim Tully, VP Distinguished Analyst Gartner Dataquest
10:30	Break
11:00	How Disruptive Technologies will Shape SoC Design and EDA Tool Development   Moderated by: Jim Tully (Gartner/DataQuest) Panelists:      - Maria Gabrani (IBM Zurich Research Laboratory)      - David Fritz (Silistix)      - Phil Dworsky (Synopsys)      - Michael Sydow (Lightspeed Logic)      - Simon Davidmann (Imperas)      - Andreas Hoffmann (CoWare)		SoC Design Platform - Bart De Loore (NXP Semiconductors)	11:00	"Soc interconnect performance verification based on hardware emulator" by Denis LEHONGRE from STmicroelectronics		IP Based Architecture - Bernard Candaele (Thales)	11:00	"An Implementation Study on Fault Tolerant LEON-3 Processor System" by Zoran Stamenkovic, Christoph Wolf & Gunter Schoof from IHP GmbH & Jiri Gaisler from Gaisler Research
				11:20	"A platform-based technology for fault-robust SoC design" by Stefano Lorenzini from YOGITECH SpA			11:20	"A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect" by Mohammad Urfianto, Tsuyoshi Isshiki, Arif Khan, Dongju Li & Hiroaki Kunieda from Tokyo Institute of Technology
				11:40	"How a retargetable tool flow for ASIP design enables SoCs for multitudes of applications" by Gert Goossens, Dirk Lanneer, Werner Geurts & Johan Van Praet from Target Compiler Technologies			11:40	"RAID6 accelerator in a PowerPC IOP SOC" by Gerard BOUDON, Haluk Aytac & John Fakiris from AMCC
				12:05	"A Platform Based SOC Design Environment" by Jeonghun Kim from Korea Univ/Mewtel Inc			12:00	"High-resolution CMOS Rotary Encoder SoC Using Magnetic Sensor Array and Statistical Angle Calculation Circuit" by Kazuhiro Nakano & Shoji Kawahito from Shizuoka Univ. & Toru Takahashi & Yoshitaka Nagano from NTN Corp.
12:30	Lunch			12:30	Lunch			12:30	Lunch
13:15	Automated Soc Assembly-dream or reality;There ARE Solutions to the Pain of IP Integration   Moderated by: Richard Wallace (Editor-in-Chief, EE Times Europe) Panelists:      - Olivier Florent (STMicroelectronics)      - Ralph Morgan (Synopsys)      - Chris Lennard (ARM)      - Dr. Satya Gupta (Open-Silicon)
			Collaborative Design - Francois Kleitz (Alcatel)	13:30	"Comprehensive Change Management for SoC Design" by Sunita Chulani & Stanley Sutton Jr. from IBM T. J. Watson Research Center, Gray Bachelor from IBM Global Business Services & P Santhanam from IBM T. J. Watson Research Center		IP Design - Paolo Pezzati (Cadence)	13:30	"IP Core for an H.264 Decoder SoC" by Wagston Staehler from UFRGS & Altamiro Susin from UFRGS
								13:45	"Silicon IP for Programmable Baseband Processing" by Eric Tell, Anders Nilsson & Christer Svensson from Coresonic
				13:50	"Light-weight Communication Infrastructure for IP Integration" by Jesús Barba, Fernando Rincón, Francisco Moya, Juan Carlos López , Félix Jesús Villanueva & David Villa from University of Castilla-La Mancha
								14:00	"1Tb/s 3W Inductive-Coupling Transceiver IP for 3D-Stacked SiP" by Noriyuki Miura from Keio University, Yoshihiro Nakagawa, Masamoto Tago & Muneo Fukaishi from NEC Corporation & Tadahiro Kuroda from Keio University
				14:10	"A Next Generation IP based collaborative Station" by Mourad Hamdoun, Brahim Missaoui & Gabrièle Saucier from Design and Reuse
								14:15	"Hardware Implementation of a Combined Interleaver and DeInterleaver" by Shyam Shenoy, Chandrashekar B U & Sayandeep Nag from Synopsys (I) Pvt Ltd
				14:30	"Unifying Diversity – A classic example of Reusability" by Gaurav Jalan from SiRF Technology & Sandeep Ahuja from SiRF Technology			14:30	"IP CORE FOR RAID 6 HARDWARE ACCELERATION" by Michael Gilroy from Institute for System Level Integration & James Irvine from University of Strathclyde & Gideon Riddell from A2E Limited
14:45	Break			14:45	Break			14:45	Break
15:15	How to Evaluate and Choose Hard IP   Moderated by: Jim Lipman Panelists:      - Michael Kaskowitz (Senior Vice President, Semiconductor IP, Mosaid)      - Larry Morrell (VP, GM IP Products, Impinj Inc.)      - Kathy Werner(VSIA & Freescale)      - Brent Dichter (ARM)      - Mary Ann White (Virage Logic)      - Mike Kliment (Mentor Graphics)		SoC Platform Forum - Peter Gillingham (Mosaid)	15:15	"STBus complex interconnect design and verification for a HDTV SoC" by Olivier CAUVET from STMicrolectronics & Francoise CASAUBIEILH from Synopsys		Mixed Signal IP - Marcello Coppola (STMicroelectronics)	15:15	"IP-based design for analogue ASICs : a case study" by Timothée Levi, Noëlle Lewis, Jean Tomas & Pascal Fouillat from IXL laboratory
				15:30	"A High Performance Platform Architecture for MIPS® Processors" by Jack Browne from MIPS Technologies, Inc.			15:30	"Fully Digital Implemented Phase Locked Loop" by Michael Gude & Gerriet Mueller from Cologne Chip AG
				15:45	"Using a Versatile, Independent IP Platform" by Jim Bruister from SoC Solutions & Bill Finch from CAST			15:45	"Deploying Mixed Signal IP - Is 'No Re-spin' Just Spin?" by Brendan Farley from Silicon & Software Systems Ltd (S3)
								16:00	"System Level design automation of pipelined analog-to-Digital Converters" by Mohamed Saeed from SWS & Mohamed Dessouky from Mentor Graphics
				16:05	"Reusable debug infrastructure in SoC prototyping: Embedded WiFi case study" by Haridas Vilakathara from NXP Semiconductors
								16:15	"Fully Digital Implemented Delta-Sigma Analog to Digital Converter" by Michael Gude & Gerriet Mueller from Cologne Chip AG
				16:25	"Developing a Reusable IP platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment" by Brendan Mullane & Ciaran MacNamee from CSRC, University of Limerick
16:30	Break							16:30	"A Unified Analog Design and Process Framework for Efficient Modeling and Synthesis" by Firas Mohamed, Yoann Courant & Stephane Bergeon from InfiniScale
16:45	Design knowledge sharing or IP reuse? Is design reuse practical and viable in an enterprise   Moderated by: Richard Wallace (EEtimes) Panelists:      - Kathy Werner (Freescale)      - David Yoon (Cisco)      - Bernard Candaele (Thalès group)      - Bill Martin (Mentor Graphics)      - Gabrièle Saucier (Design and Reuse)      - Frédéric Joly (TES Electronic Systems)			16:45	Break			16:45	Break
			IP Protection - Provider Selection - Phil. Dworsky (Synopsys)	17:00	"A Security Tagging Scheme for Application Specific Intellectual Property Cores" by Carol Marsh from iSLI / Algotronix & Tom Kean from Algotronix		IP Design / Physical Design - Paolo Pezzati (Cadence)	17:00	"Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core" by Cyril Prasanna Raj P from MS Ramaiah School of Advanced Studies
								17:15	"Integrating PCI Express IP in a SoC" by Ilya Granovsky & Elchanan Perlin from IBM
				17:20	"Protecting IP in a Modern Design Flow" by Dan Moritz from Virage Logic & Saverio Fazzari
								17:30	"BACK-END TOOL FLOW FOR COARSE GRAIN RECONFIGURABLE IP BLOCK RAA" by Tapio Ristimaki, Claudio Brunelli & Jari Nurmi from Tampere University Of Technology
				17:40	"High Performance Connectivity IP – Avoiding Pitfalls When Selecting An IP Vendor" by Navraj Nandra from Synopsys
								17:45	"Top Down SoC Floor planning with ReUse" by Fuad Abu Nofal & Monica Nofal from ChipEDA
18:00	Partner Organization OCP-IP - Update by Ian Mackintosh from OCP-IP “A Quick Introduction to FSA…” by Pietro Provolo from FSA Europe VSIA - Update by Kathy Werner from the VSI Alliance			18:00				18:00	"MpNoC Design: Modeling and Simulation" by Simon DUQUENNOY, Sébastien LE BEUX, Philippe MARQUET, Samy MEFTALI & Jean-Luc DEKEYSER from INRIA Futurs, Lille
								18:15	"Realizing the Performance Potential of a PCI Express IP" by K Yogendhar, Vidhya Thyagarajan & Sriram Swaminathan from Rambus Chip Technologies (Pvt) Ltd.
								18:30
18:45
19:30	Departure for the banquet

DAY 2: December 7, 2006

AUDITORIUM			ROOM 1				ROOM 2
Time	Panel		Session	Time	Paper		Session	Time	Paper
8:00	Standard for automotive - Warren Savage (IPEXTREME) "Using IP to Accelerate the Adoption of New Automotive Standards" by Warren Savage from IPEXTREME "Open Source FlexRay Communication: Time Triggered OS" by Hiroyuki Hattori, Shuichi Ohnisi & Akihisa Morikawa from Witz Corporation, Kazuhiko Nakamura from Sunny Giken Inc. & Hiroaki Takada from Nagoya University "FlexRay – The Hardware View" by STEFAN SHMECHTIG from IPEXTREME "eVerification Environment for FlexRay Advanced Automotive Networks" by Stefan Schmechtig from IPEXTREME
			Validation - Test - Alain Greiner (University of Paris 6)	8:15	"High Density FPGA Package BIST Technique" by Douglas Goodman, James Hofmeister & Justin Judkins from Ridgetop Group Inc.		Network on Chip - Huy Nam Nguyen (Bull)	8:15	"A Heuristic Energy Aware Application Mapping algorithm for Network on Chip" by Armin Mehran from Iran Telecom Research Center/Azad University, Science & Research Campus & Ahmad Khademzadeh from Iran Telecom Research Center & ALi Afzali Kousha from ECE department of Tehran University Babak Shirpour from Azad University, Science & Re
				8:30	"A Python based SoC Validation and Test Environment" by Nicolas Tribie & Olivier Fargant from Wipro-Newlogic			8:30	"A Central Caching Network-on-chip Communication Architecture Design" by Nan Wang, Sanusi Azeez & Magdy A. Bayoumi from University of Louisiana at Lafayette
								8:45	"Synthesizable Switching Logic for Network-on-Chip Designs on 90nm Technologies" by Tapani Ahonen & Jari Nurmi from Tampere University of Technology
				8:50	"Remote Testing and Diagnosis of System-on-Chips using Network Management Frameworks" by Oussama Laouamri & Chouki Aktouf from DeFacTo Technologies
9:00	Break							9:00	"GA based Intelligent Packet Routing to support QoS in MANET" by Sonal Popat from ISTAR - S.P. University & Darshan Amrutia from ISTAR - S.P. University
				9:10	"Re-Use of Unit level verification framework" by Aniruddha Baljekar from NXP Semiconductors
9:15	Standards and Wrappers - Pierre Bricaud (Synopsys) "IP encapsulation: Approach and Case Study" by Fatma Abbes from ENIS, Emmanuel Casseau from LESTER & Mohamed Abid from ENIS "TLM status update" by James Aldis from TI "A generic Spirit compliant Loose Generator interface" by Gabiele Saucier, Lassaad Ghanmi & Karima Skiba from Design And Reuse "IPZIP - AN IP DISTRIBUTION FRAMEWORK" by Cristiano Araujo, Edna Barros & Millena Gomes from UFPE & Guido Araujo from Unicamp							9:15	"Methods of selection of structural and architectural organization of multicast switches" by Yury Sheynin & Ellin Suvorova from Saint-Petersburg University of Aerospace Instrumentation
				9:30	Break			9:30	Break
			Verification - Steve Leibson (Tensilica)	9:45	"USB2 PHY Verification" by Hugo Cavalcanti & Gary Miller from Freescale Semiconductor			9:45	Design for Debug (DFD) and Design for Test (DFT)   Organized by: Anish Kumar (Dear Born Electronics India Bangalore) Panelists:      - Michel Depeyrot (Dolphin-Integeration)      - Anthony Berent (ARM)      - Pramesh Dahiya (Integramicro System Pvt Ltd)      - Doug Goodman (Ridgetop Group)      - Denis Rousseau (Temento)
				10:05	"A New Methodology for Hardware Software Co-verification" by Venkata Giri Kumar, Manoj Ariyamparambath & Bashuman Deb from Synopsys (India) Pvt Ltd
10:15	Design flow integration with IP-XACT from The SPIRIT Consortium : from proof point to industrial adoption   Moderated by: Pierre Bricaud (Synopsys) Panelists:      - Loic Le-Toumelin (SoC Development Methodology, Wireless Cellular Systems, TI)      - Gabriele Saucier (Design And Reuse)      - Wolfgang Ecker (Principal Engineer, Infineon)      - Xavier Caron (Design Flow Engineer, ATMEL)
				10:25	"Development of Verification Environment for Layered Protocol using SystemVerilog" by Ganesh Dekate from Infineon Technologies
				10:45	Break
								11:00	Break
11:15	Reconfigurable IP/SoC and power consumption   Moderated by: Paul Holt (Vice President of Customer Support, ARC International) Panelists:      - Andreas Hoffman (Founder of LISATek and Engineering Director, CoWare)      - Steev Wilcox (Founder and Chief Architect, Azuro)      - Sean Redmond (Vice President of European Sales and Customer Support, Cadence)      - Yatin Trivedi (Director of Industry Partnerships, Magma)      - John Swanson (Director of IP Solutions, Synopsys)      - Jeremy Bennett (Tension)		Protoyping - Bill Martin (Mentor Graphics)	11:15	"FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies" by Kodavalla Vijay Kumar & Singh Devendra Bahadur from Wipro Technologies		High level model and design Forum - Kathy Werner (Freescale)	11:15	"XML-Based Assertion Generation" by Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger & Michael Velten from Infineon Technologies AG
				11:35	"Fast Virtual Prototyping for early software design and verification" by Amit Garg from CoWare			11:35	"Accelerated IP Model Development" by Bill Neifert from Carbon Design Systems
				11:55	"Practical Applications of Data Abstraction Techniques for Embedded Systems Debug" by George Bakewell from Novas Software, Inc. & Charles Janac from Arteris			11:55	"Design of a C library for the implementation of 3D graphics applications on a SoC" by Fabio Garzia, Claudio Brunelli, Juha Killiainen & Jari Nurmi from TUT
				12:15	"An Analog Verification and IP Development Environment" by Stephan Weber from Cadence			12:15	"System on Chip Development. How to put into practice a "Submit, Integrate, Test and Release" Methodology." by Felix Beniamin from ENOVIA MatrixOne
12:30	Lunch and Best Prize			12:30	Lunch and Best Prize			12:30	Lunch and Best Prize
13:30	Integrating Nonvolatile Memory in SoC Designs: Save Time and Reduce Design Costs   Moderated by: Jim Lipman (Cain Communications) Panelists:      - Larry Morrell (VP, GM IP Products, Impinj)      - Craig Rawlings (Kilopass Technology)      - Pierre Fazan (Founder & CTO, Innovative Silicon)      - Rick Shen (eMemory Technology)      - Peter B. Gillingham (Vice President and Chief Technology Officer, Mosaid)      - Xerxes Wania (President and CEO, Sidense)		High level / TLM - Chris Lennard (ARM)	13:30	"Distributed software behaviour analysis through the MPSoC design flow" by Julien Bernard from INRIA/MOAIS, Serge De Paoli from STMicroelectronics & Fabrice Salpetrier from IMAG/LSR		Industrial approaches in Verif / Proto - Helena Krupnova (ST Microelectronics)	13:30	"A Unified CPU Modeling for SoC Verification" by RAVI KUMAR AVUDAI NAYAGAM from HCL Technologies Ltd.
				13:50	"Transaction Recording, Modeling and Extensions for SystemVerilog" by Rich Edelman, Mark Glasser, Chris Cotterel & Bill Cox from Mentor Graphics			13:50	"Measurable Verification Methodology for Highly Configurable IP Cores" by Vishal Namshiker from Synopsys
				14:10	"Increasing System-on-Chip reusability using Hardware Abstraction Layer" by Raghawendra Singh from BITS Pilani			14:10	"Verification planning for Reusable core based designs" by Anjali Vishwanath & Ranga Kadambi from Infineon Technologies Asia Pacific Pte Ltd
				14:30	Break			14:30	"Improving ASIC Design Verification using FPGAs and Structured ASICs" by Pat Mead from Altera
								14:50	Break
15:00	Break		Design and Test Forum - Denis Rousseau (Temento)	15:00	"IP reliability and the evaluating technology" by Luo Hongwei, En Yunfei & Xiao Qingzhong from China Electronic Product Reliability and Environmental Testing Research Institute
15:15	Network on Chip   Moderated by: Huy Nam Nguyen (Bull S.A.S.) Panelists:      - K. Charles Janac (Arteris)      - Alain Greiner (UPMC/LIP6)      - John Bainbridge (Silistix)      - Marcello Coppola (ST-Microelectronics)      - Oliver Bringmann (FZI)      - Fabien Clermidy (CEA/Leti)			15:15	"PROCESSOR DESIGN AND IMPLEMENATION FOR REAL-TIME TESTING OF EMBEDDED SYSTEMS" by shyam Akashe from ITM & Yagendra Gupta from ITM
							Design Forum - Joseph Borel (JB-R&D)	15:20	"Delivering Solutions for 90nm for RF CMOS, Analog and High-speed Circuit Design" by Alain MICHEL from ANSOFT
				15:30	"Silicon validated IP cores designed by the Brazil-IP Network" by Ana Karina Rocha from UFCG & Patricia Lira from UFPE & Yang Yun Ju from UNICAMP Elmar Melcher from UFCG & Edna Barros from UFPE
								15:35	"Transaction Level Model of the USB On-The-Go controller IP core" by Marek Podeszwa & Filip Rak from Evatronix SA & Wojciech Sakowski from Silesian University of Technology
				15:45	"Smart Interconnects with Smart IP" by WARREN Savage from IPEXTREME & Jeff Haight from Sonics
								15:50	"RFID Radio Circuit Design in CMOS" by Alain MICHEL from ANSOFT
				16:00	"Design and real time hardware implementation of a generic fuzzy logic controller for a transport/diffusion system" by Sukrit Shankar from Conexant Systems India Pvt. Ltd. & Jaydev Sharma from IIT Roorkee & Shamim Akhtar from JIIT, Noida & Chetana Shanta Patsa from IBM,India
								16:05	"IPextreme Solution" by WARREN Savage from IPEXTREME
				16:15
								16:20
16:45

• "A Multi-Objective Optimization Model for Energy and Performance Aware Synthesis of NoC Architecture" by Rabindra Jena from IMT & Gopal Sharma from ABV-IIITM
  
  
• "APPLIED CRYPTOGRAPHIC SCHEMES" by Lev Drannikov from Canadian Data Security
  
  
• "Audio Coding for Wireless Applications" by Stephen Wray from APT
  
  
• "Domain Specific System On Chip Architectures for IP" by SESHA GIRI RAO MADDALA from Department of Information Technology
  
  
• "Low power 7T SRAM cell scheme - Saving write Zero power" by Anita Mkumari from Mtech Punjab University & Prof J.N. Roy from Punjab University
  
  
• "Hard IP Core Placement Method in VLSI Physical Design" by Zhe Feng, LiGang Hou, Wei Wang, Cheng Liu & WuChen Wu from Beijing University of Technology
  
  
• "Placement Constraints handling for VLSI Floorplan Design using Genetic Algorithm" by Vasudev Dehalwar & Yogendra Kumar from MANIT
  
  
• "SIMULATOR OF THE BEHAVIOR OF THREE-PHASE VOLTAGE REGULATORS BANKS USED IN DISTRIBUTION SYSTEM OF ELECTRIC ENERGY" by Manoel Firmino de Medeiros Jr, Jose Alberto Nicolau de Oliveira, Max Chianca Pimentel Filho, Marcos Antonio Dias de Almeida & Janio Mendonça Jr from UFRN
  
  
• "Predictable Paths to Satisfying Design Targets" by Paul Nottingham from Zenasis Technologies
  
  
• "Genetic algorithm for high level analysis and architecture exploration" by Issam MAALEJ, Guy Gogniat & Jean Luc Philipe from LESTER / UBS