IP / SoC 2006 - Reconfigurable IP/SoC and power consumption

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Reconfigurable IP/SoC and power consumption

Moderated by: Paul Holt, Vice President of Customer Support, ARC International

Panelists:
     - Andreas Hoffman, Founder of LISATek and Engineering Director, CoWare
     - Steev Wilcox, Founder and Chief Architect, Azuro
     - Sean Redmond, Vice President of European Sales and Customer Support, Cadence
     - Yatin Trivedi, Director of Industry Partnerships, Magma
     - John Swanson , Director of IP Solutions, Synopsys
     - Jeremy Bennett, Tension

According to industry analysts, by 2010 there will be 1 billion system-on-chips (SoCs) incorporating a configurable 32-bit processor shipping to market annually. This represents a 45% CAGR growth rate, which outpaces the predicted 10% CAGR of SoCs containing a 32-bit fixed architecture core.

Battery operated consumer applications are driving the adoption of configurable CPUs. A key reason is the ability of configurable architectures to consume less power than non-configurable alternatives. This benefit is extended by SoC design solutions optimized for configurable instruction set architectures, such as high-level simulation tools, integrated RTL to GDS II flows, and other techniques for nanometer designs.

This panel will explore the ability of configurable architectures and integrated SoC design solutions to lower power consumption in SoCs. The panel will include technical representatives from companies such as ARC International, Cadence Design Systems, Magma, CoWare, Azuro, Tenison, and Synopsys.