Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore
Home/Introduction
Program Committee
Exhibition
Conference Program
Pratical Information
Training & Tutorials

Design knowledge sharing or IP reuse? Is design reuse practical and viable in an enterprise

 
Moderated by:



Richard Wallace
Editor-in-Chief
EE Times Europe
Panelists:
     - Kathy Werner, Freescale
     - David Yoon, Cisco
     - Bernard Candaele, Thalès group
     - Bill Martin, Mentor Graphics
     - Frederic Joly, TES Electronic Systems
     - Gabrièle Saucier,  Design and Reuse

This panel will address the following questions about IP based collaborative design in an Electronic design house

  • How to store ,archive the company assets in terms of block design .
  • Is the reuse station concept viable at the corporate level? Or Is it more relevant at an application specific or technology platform level
  • Is the most attractive feature the knowledge sharing in terms of design skills ,design practice, experience, testimonials rather than reusable blocks themselves
Testimonials from companies which have tried ,succeeded or failed will lead to an analysis of success /failure factors