IP / SoC 2006 - How Disruptive Technologies will Shape SoC Design and EDA Tool Development

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How Disruptive Technologies will Shape SoC Design and EDA Tool Development

Moderated by:

Jim Tully, VP Distinguished Analyst
Gartner Dataquest

Panelists:

		Maria Gabrani IBM Zurich Research Laboratory			David Fritz Silistix
		Phil Dworsky Synopsys			Michael Sydow Vice President Customer Engineering Lightspeed Logic
		Simon Davidmann Imperas			Andreas Hoffmann CoWare

EDA tool flow, and hence tool development, is reasonably consistent over time, with most changes being incremental in their influence on the overall chip design flow. However, there are instances when a disruptive technology results in a major change in the way that tool vendors develop and introduce their products and how designers use these tools. Examples include logic synthesis two decades ago, Structured ASICs and, more recently, the introduction of yield enhancement and DFM tools into the design flow.

This panel will discuss several disruptive technologies and how their acceptance and use will influence the tools and design methodologies chip designers will need down the road.