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Free Tutorial - Nanometer MPSOC Design Using Configured CoresTuesday 5 December, 2006 [11h00 - 13h00] Steve Leibson Tensilica, Inc. SUMMARY This two-hour tutorial is aimed at researchers and designers involved with complex SOC design who need to understand how to develop complex, mega-gate SOCs under severe time and cost constraints. Managers at companies making significant investments in SOC designs and platforms will also find the information in this tutorial essential to making decisions regarding the changes they may need to make in investment strategies, core competencies, and organization structure over time. This presentation emphasizes a processor-centric MPSOC (multiple-processor SOC) design style consistent with the realities of 21st-century, nanometer silicon. Assignment of on-chip tasks to firmware-controlled processor cores whenever possible maximizes SOC flexibility, cuts power dissipation, reduces the size and number of hand-built logic blocks, shrinks the associated verification effort, and thus minimizes overall design risk. The tutorial outlines the major forces changing today’s SOC design process, and introduces the concept of SOC design using configured and configurable processors as a basic design fabric. A family of software-compatible, configurable and configured microprocessor cores can efficiently implement a wide range of simple control, conventional DSP, and media-processing tasks while employing a consistent set of software-development tools so that programmers familiar with one processor in the family can easily switch to another. The tutorial also covers the advantages and disadvantages of various on-chip interconnect schemes such as bus hierarchies, networks on chip (NoCs), and direct point-to-point communications. It uses several examples with different flavours of extensibility and scalability to give a precise, practical, and up-to-date picture of the real issues and opportunities associated with this new design approach. The tutorial concludes by looking down the road at the longer-term future of SOC design, examining basic trends in design methodology and semiconductor technology. It paints a 10-15 year outlook for the qualitative and quantitative changes in design, in applications, and in the structure of the electronics industry. AUTHOR BIO Steve Leibson is the Technology Evangelist at Tensilica, Inc. He an experienced hardware and software design engineer, engineering manager, and design consultant. He spent 10 years working at electronic systems companies including HP’s Desktop Computer Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA workstations) after earning his BSEE cum laude from Case Western Reserve University. He then spent 15 years as an award-winning technology journalist, publishing more than 200 articles in Microprocessor Report, EDN, EE Times, Electronic News, and the Embedded Developers Journal. Leibson has just written and published “Designing SOCs with Configured Cores,” a treatise on 21st-century MPSOC designs. Leibson is an accomplished speaker, having given many presentations at SOC-design and EDA conferences in countries around the world including the US, France, Germany, China, and Finland. He is an IEEE Senior Member.
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