Glossary of Terms
Source:
ARM Ltd, Cheshire Henbury, EETimes, OCP-IP, Palmchip Corp, Sonics
Inc., VSI Alliance
Status: work in progress
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full glossary
A
Agent: A module of a SMART Interconnect that is a communication
interface between the core and the interconnect’s internal logic. The collection
of all agents, plus the internal logic between them, constitutes the logic
of an interconnect.
Agents decouple the SoC’s componentized cores by translating between the
OCP and interconnect protocols. There are a variety of different agents
including target and initiator agents.
AHB: Advanced High speed Bus, synchronous pipelined bus architecture
from ARM.
AMBA: The Advanced Microcontroller Bus Architecture (see www.arm.com).
APB: Advanced Peripheral Bus, synchronous, easy-to-use bus architecture
for peripherals from ARM.
Arbitration: The process of prioritizing and controlling transfer
of communication signals between System-on-Chip functional blocks. More specific:
The logic and protocol that determines which entity owns a bus or a shared
path at a specific time.
Architecture: A formal framework that defines the interconnection
of cores for a system-level design. Architectures enable many designers to
follow a standards-based implementation.
ASIC (Application Specific Integrated Circuit): Pronounced "A-sick."
A chip that is custom designed for a specific application. ASICs are often
designed for only one customer rather than as a general-purpose chip such
as a microprocessor. ASICs improve performance over general-purpose CPUs,
because ASICs are "hardwired" to do a specific job. They do not incur the
overhead of fetching and interpreting stored instructions. An ASIC chip performs
an electronic operation as fast as it is possible to do so, providing, of
course, that the circuit design is efficiently architected.
ASP (Average Selling Price): The sum of all the prices of a group
of products divided by the number of products used in the list.
ASSP (Application Specific Standard Product): - A relatively new
term for ICs targeting specific types of systems. In many cases the IC will
be manufactured using ASIC technology but will ultimately sold as a standard
device type to numerous users (i.e. put in a product catalog). If the end-user
helped the IC producer design the ASSP, that user is typically given a market
lead-time (i.e. window of opportunity) to use the device before it is made
available to its competitors.
B
Bandwidth: Communication capacity. It is typically referred to
when characterizing data transfer rates.
Block: The basic SoC building block. Blocks (sometimes known as
cores) can be sourced internally or be commercially supplied.
Broadcast: A bus transmission that is meant to be received by more
than one destination.
Bus:
Definition:
- Passive wire-based Interconnect on a semiconductor device
- Processor Centric: IP blocks are expected to understand the bus' protocol
and pipelining style; System requirements are reflected back into the IP
- A major pathway for moving signals—data flow, control flow, test flow—between
functional blocks in an SoC or between multiple ICs. Traditionally
it is associated with a CPU block or peripheral block in the context of SoC
design.
Common Characteristics:
- Data is broadcasted to all nodes at the same time
- Blocking Transaction Protocol used by shared; multiple, or hybrid buses:
- Shared bus: Common way to move on-chip data; Large Multiplexer selects
the source and drives a single interconnect net, which sends the signal to
all devices on the bus; Only one device can drive the bus at a time
- Multiple Buses: Separate buses serve individual initiators to increase
bandwidth and connectivity; Bridges are used between segments (Multi-layer
busses); Targets are addressed via initiator bus specific multiplexer
- Hybrid Topology: Separate buses and point to point connections; These
architectures cluster tightly coupled computational units with high communication
bandwidth and provide lower bandwidth inter-cluster communication links
C
CDMC (Consumer Digital Multimedia Convergence):
"The convergence of digital Set-Top Box (STB) technology, digital broadcast
satellite, residential gateways, and games is leading to a battle for the
digital living room. More and more features like personal video recording
(PVR), Video on Demand (VoD), broadband Internet access, DVD/CD playback,
interactive gaming, MP3 audio, digital audio and video content storage, and
home networking (wired and wireless) will be supported by one device.
Systems-on-a-Chip addresses the need to manage the increasing design complexity.
It exists a continued pressure to reduce design cycle time and to reduce
NRE, which are the driving factors of today's SoC developments.
Control Flow: The signal flows between SoC functional blocks that
initiate actions such as data transfers.
Core: A complete IP deliverable, including the building blocks,
related software and test-benches. It is a complex, pre-designed function
that will be integrated onto a larger chip.
CoreConnect™: The CoreConnect™ bus provides the primary means of
communication between macros in an IBM Blue Logic™ design.
CoreFrame® architecture: The architecture, patented by Palmchip,
consisting of a high performance, point-to-point interconnection scheme for
the easy integration of IP into an SoC. It is foundry, I/O, and processor
independent, and supports 8-,16-, 32- and 64-bit peripherals.
CPU (Central Processing Unit): The computing part of the computer.
Also called the "processor," it is made up of the control unit and the arithmetic
logic unit (ALU). Today, the CPUs of almost all computers are contained on
a single chip. The CPU, clock and main memory make up a computer. A
complete computer system requires the addition of control units, input, output
and storage devices and an operating system.
D
Data Flow: The data traffic between SoC functional blocks.
Decoupled or decoupling: A quality of SoC integration that promotes
independence and core reusability. Agents decouple the cores from each
other as well as from the interconnect. This enables the block integration
process to be automated and ensures core reusability.
DMA (Direct Memory Access): Method by which data is read or written
from shared memory by hardware proxy. This may be initiated by firmware or
performed automatically.
DMA Channel: In an SoC, an intelligent burst device that transfers
data between shared memory and another SoC device. Note: A channel can include
intelligent devices which access memory without affecting data transfer,
and may include devices that transfer data from one portion of shared memory
to another.
DRAM (dynamic RAM): The most common type of computer memory, also
known as D-RAM. Usually uses one transistor and a capacitor to represent
a bit. The capacitors must be energized hundreds of times per second in order
to maintain the charges. Unlike firmware chips (ROMs and PROMs for example)
both major varieties of RAM (dynamic and static) lose their content when
the power is turned off. Contrast with static RAM
DSP (Digital Signal Processor): A DSP is a special-purpose CPU
used for digital signal processing. It provides ultra-fast instruction sequences,
such as shift and add, and multiply and add, which are commonly used in math-intensive
signal processing applications. DSP chips are widely used in a myriad of
devices, including sound cards, fax machines, modems, cellular phones, high-capacity
hard disks, and digital TVs
I
IC (Integrated Circuit): The formal name for a micro-chip.
Initiator/Target (Master/Slave): An Initiator is a functional block
that initiates transactions within the SoC. Initiators are commonly software
programmable such as CPU or DSP cores. They control one or more other devices
or (known as targets). Once the Initiator/Target relationship is established,
the direction of control is always from the Initiator to the Target(s).
Interconnect: Interconnect is the medium within an SoC (or standard
IC) that serves to transfer data, control and test signals between functional
blocks.
Interface Standards:
Definition:
- A format and language (description of signals and protocol) that defines
the services one system is capable of delivering to another
- It is not a Bus or a MicroNetwork – it is an interface that allows
interoperable connection of virtual components to major on-chip busses and
MicroNetworks in the industry to ensure rapid creation and integration of
interoperable virtual components
- Common Standards for intellectual property (IP) core interfaces, or
sockets for interfacing IPs with on-chip buses and MicroNetworks to support
IP re-use
- Usually the standards define:
- A protocol for the transfer of requests and responses
- The contents and coding of these requests and responses
- Usually do not touch areas such as arbitration
Common characteristics:
- Allows SoC designers to connect cores from different IP vendors to
rapidly create a System-on-a-Chip
- Standardized interfaces replace the need to create the costly and time
consuming highly customized interfaces required in bus-based designs
Interrupt: An out-of-band communication that would typically cause
a processor to temporarily halt the routine it is executing and call another.
IP (Intellectual Property): Technology that can be licensed to
enable the creation of an SoC. The IP may include source code for creation
of hardware or software, compiled code, and implementation instructions.
L
Latency: The response time required by the communication system
to make a signal transfer between SoC functional blocks.
M
Master: See “Initiator, Target”
Memory Controller: A device that controls shared memory and accepts
requests for memory access from one or more channels.
MicroNetwork (active interconnect):
Definition:
- Active circuits, on a semiconductor device whose purpose is to manage
information flows between functional portions of that semiconductor device
- Independent operation from functional blocks
- Processor agnostic
- Communication centric: Management of the information flow using techniques
that are not necessarily those used by any of the functional - decouples
the interconnect from the sub-systems (IP cores)
- Inter-core communication systems relying on standard protocol stacks
to communicate between devices
Common Characteristics:
- Non-blocking interconnect architecture using a split-transaction protocol
to communicate between sub-systems on chip
- Scalable, highly configurable inter-core communication system;
- Guarantees end-to-end performance and real-time quality of service.
- Adapts itself to the needs of the IP cores in the system and not vice
versa
- Supercedes classical bus architectures
Moore's Law: states that the increase in complexity of microprocessors
and other types of semiconductor integrated circuits will double every 18
months. History shows that so far this has been the case, and in fact the
observation made by Gordon Moore has become a self-fulfilling prophecy.
This doubling in complexity has resulted in a phenomenal growth in the amount
of computing power available on a single microprocessor chip. However, the
cost of developing these chips and providing production facilities is also
growing, and the profits from one generation of chips are needed to finance
the development of the next generation.
There is a problem referred to as a “design gap”. Design productivity is
increasing more slowly than the complexity and capabilities of the technology.
Among industry insiders, this is known as the "productivity gap." This refers
to the problem that while chip makers sport state-of-the-art tools for manufacturing
highly complex chips, their design tools and engineers are unable to keep
pace by designing chips of that magnitude.
This means that in some cases, companies that commit millions of dollars
in resources and man-hours to design a new microchip will find that their
product is obsolete even before it hits the market, say some industry experts.
Gordon E. Moore first laid down his law in 1965, eight years after he co-founded
Fairchild Semiconductor and three years before he helped create Intel.
MPEG (Moving Pictures Experts Group): Pronounced "em-peg." An ISO/ITU
standard for compressing video.
N
Non-posted write: A write command that requires a response from
the target
O
OCB: On Chip Bus
OCP (Open Core Protocol): A new, open, point-to-point interface
standard that allows IP cores to be designed and operated independently.
It enables IP blocks to become componentized cores in order to be designed
independently from each other and from the interconnect structure. OCP is
promoted via the non-profit organization OCP-IP (Open Core Protocol International
Partnership, www.ocp-ip.org).
P
Platform: Pre-integrated, pre-verified collection of IP, ideally
consisting of processor support functions, application-specific control logic,
memory control, and any required on-board memory. May also include software.
Port: The input or output points of a module or instance.
Q
Quality of Service (QoS) Guarantees: The requirements of
any given block for timely delivery of data and/or control information and/or
sustained access to another block. In many applications, this must
be met to ensure the proper operation of the IC. These guarantees are traditionally
met by using bus structures as a basis and then applying design resources
to modify blocks and/or add wires and logic until the full set of service
requirements are met.
S
Set-top Boxes: are called by several names: “boxes,” STBs, set-tops,
cable/satellite boxes, receivers, and converters. They all mean the same
thing – a stand alone box designed to sit atop a TV, receive a special signal
(non-broadcast or terrestrial), condition that signal, and present it to
the TV set.
The Digital Set-top Boxes control and decode compressed television signals
for digital satellite systems, digital cable systems, and digital terrestrial
systems. Digital STBs represent a fast-growing market for video and audio
compression and processing devices, which are sold today as ASICs but are
rapidly moving away from ASIC technology toward application-specific standard
products (ASSPs).
In the future, STBs are likely to be used for Web browsing. High-bandwidth
Internet access will be widely available to consumers in industrial nations
by 2002, motivating existing buyers to increase annual spending for Internet
access. Digital cable boxes will help make this a reality. The primary type
of video compression used in both cable and satellite systems are MPEG-2.
For audio, the MPEG and AC-3 standards are used.
In addition to decompression, digital STBs perform a variety of video and
audio processing, including de-multiplexing, graphics control and acceleration,
and NTSC/PAL encoding. Compression drives the use of more semiconductors
in the box, since many of these functions are performed on a single-chip
ASSP, and video decompression usually requires about 2MB of DRAM.
Sideband Signals: Optional signals that are not part of the data
flow. The signals typically convey control information such as reset, interrupt,
error, and core-specific flags.
SiliconBackplane MicroNetwork™: Sonics’ patented engineered inter-core
communications system. The SiliconBackplane manages to meet the needs
of the functional blocks rather than modifying the blocks to work around
the capabilities of the interconnect. (Sonics refers to this attribute as
decoupling the blocks.) The SiliconBackplane is a hybrid communications solution
marrying the efficient data transfer capabilities of computer-style buses
together with the quality of service guarantees from communication-centric
bus structures.
Slave: See “Initiator,Target”.
SMART Interconnect: Sonics’ heterogeneous, integrated network-on-a-chip
that unifies, decouples, and manages all communications between processors,
memories, and input/output devices. Sometimes referred to as MicroNetwork
or Interconnect.
SoC: SoC is an acronym for System-on-a-Chip. The electronics for a
complete, working product contained on a single chip. While a computer on
a chip includes all the hardware components required to process instructions,
an SoC includes the computer and all required ancillary electronics. For
example, an SoC for a telecom application might contain a microprocessor,
digital signal processor (DSP), RAM, and ROM.
Benefits of SoCs:
- Design of more functions on a single chip reduces the cost per function
and enables the development of more sophisticated devices at prices that
can survive in a consumer market;
- Increased integration reduces the size of the end product, which is
pertinent given the rise in the number of e.g. handheld devices and the trend
in reducing their size;
- Integrated circuits are more reliable than a collection of components
– improved integration means improved reliability;
- Integrated devices tend to consume less power than a collection of
components;
Socket: Standardized interface to which an SoC peripheral core
may connect to an SoC system. For example, this may be the interface between
a peripheral core and a DMA Channel.
Stimulus: Commands or instructions that exercise the logic of a
design. Stimulus can include behavioral models that exercise particular signals
or an exact specification of input values for those signals at specific simulation
times.
Synapse™3220 SMART Interconnect: Sonics’ product name for their secondary
interconnect; An on-chip interconnect serving a large number of peripheral
IP cores that are physically dispersed across the die of a chip. Sometimes
abbreviated as s3220 or Synapse 3220.
T
Target: See “Initiator, Target”
3G (Third Generation wireless): Digital plus high-speed data and
global roaming. Known as IMT-2000 by the ITU and implemented in Europe as
UMTS and CDMA2000 in North America. Goals are high-quality multimedia and
advanced global roaming (in-house, cellular, satellite, etc.).
Time Division Multiple Access (TDMA): A scheme for sharing interconnect
by parceling its availability into time slices.
Threads: A request sequence that always maintains its order.
That is, a thread never has out-of-order request delivery, execution, or
responses. Threads allow the inherent concurrency available in the cores
to be represented. This is typically done to avoid performance loss. Without
threads, multiple concurrent request sequences must be interleaved and time
multiplexed into one sequence. Any delays encountered by any request impacts
all requests after it, and therefore all concurrent sequences. By labeling
each request as belonging to a distinct thread, the target core is free to
re-order execution in order to optimize.
Transaction: One or more related transfers that are linked together
in a burst to guarantee functionality or improve performance.
Transfer: A command that can move up to one word of data.
Transfer phase: Sequential elements of a transfer.
V
VC: Virtual Component
VC: Virtual Component
VCI: Virtual Component Interface, a standard released by VSIA for
the bus architecture- and protocol neutral interconnection of IP components.
VSIA: Virtual Socket Interface alliance, an organization formed
to promote the adoption of standards for design of advanced ICs with reusable
IP.
W
Wrapper: Logic that encapsulates a core and converts its signaling
protocol to a standardized interface protocol.
