Definition
- Passive
wire-based Interconnect on a semiconductor device
- Processor
Centric: IP blocks are expected to understand the bus' protocol and
pipelining style; System requirements are reflected back into the IP
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Common
Characteristics
- Data is
broadcasted to all nodes at the same time
- Blocking
Transaction Protocol used by shared, multiple, or hybrid buses
- Shared
bus: Common way to move on-chip data. Large Multiplexer selects
the source, and drive a single interconnect net which sends the signal
to all devices on the bus. Only one device can drive the bus at a time
- Multiple
Buses: Separate buses serve individual initiators to increase bandwidth
and connectivity; Bridges are used between segments (Multi-layer busses);
Targets are addressed via initiator bus specific multiplexer
- Hybrid
Topology: Separate buses and point to point connections; These architectures
cluster tightly coupled computational units with high communication
bandwidth and provide lower bandwidth inter-cluster communication links
Available
Solutions
Commercially
available:
Alternative Solutions
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