Design Reuse Feedback | D&R Products | Site Map | Register | MyD&R
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore

DAY 1: November 13, 2003


Room1




































































































































Room 2
Session Time
 Paper Session
 time
 Paper
  8:00     8:00  

8:05

8:05

8:10

8:10  



8:15 Welcome by Gabriele Saucier


8:15  
8:20
8:20  
8:25
8:25  

8:30 "Recent Trends in Multi-Million-Gate Multimedia SOC Designs" by Santanu Dutta, IC Design manager at Philips Semiconductors (U.S.A)
8:30  
8:35
8:35  
8:40
8:40  
8:45
8:45
  
8:50
8:50  
8:55
8:55  
9:00 "Design platform for IP based SOC design" by Ted Vucurevich , CTO of Cadence (USA)
9:00
  
9:05
9:05  
9:10
9:10  
9:15
9:15  
9:20
9:20  
9:25
9:25  
9:30 "The IP Provider Game: Size and Diversity Do Matter" by Raul Camposano, CTO of Synopsys (USA)
9:30  
9:35
9:35  
9:40
9:40  
9:45
9:45
  
9:50
9:50  
9:55
9:55  
10:00 "Dataquest IP business analysis" by Jim Tully from Gartner / Dataquest (UK)





10:00  
10:05
10:05  
10:10
10:10  
10:15
10:15  
10:20
10:20  
10:25
10:25  






10:30
COFFEE BREAK





10:30 COFFEE BREAK
10:35 10:35
10:40 10:40
10:45 10:45
10:50 10:50
10:55 10:55
11:00 "Increased Verification productivity through extensive reuse" by Giles Hall from Verisity Design (UK)





11:00 "Selecting the Right Cell Library IP for Nanometer Technology" by Mike Colwell & Gene Sluss from Virage Logic (USA)
11:05 11:05
11:10 11:10
11:15 11:15
11:20 "Functional Verification of a CAN Data Layer Implementation: A Case Study" by A. Souza, J. Sabino & P. Domingues from Motorola (Brazil) 11:20 "Mixed Signal SoC Applications" by Ron Landry from AMI Semiconductor  (USA)
11:25 11:25
11:30 11:30
11:35 11:35
11:40 "A Toolkit for Rapid Modeling, Analysis and Verification of SoC Designs " by R. Deaves & A. Jones from SuperH (UK) 11:40 "Maximize Design Flexibility with Fast Turnaround Time while Minimizing Design Costs with Metal Programmable Libraries" by D. Sherlekar, O. Siguenza & H. Yang from Virage Logic (USA)
11:45 11:45
11:50 11:50
11:55 11:55
12:00 "System C Verification, Simulation & Emulation of Secure Digital IP" by Ken Reid from Cadence Design Systems (UK) 12:00 "‘A la Carte’ SoCs require innovative IO management" by David Murray from Duolog Technologies (Ireland)
12:05 12:05
12:10 12:10
12:15 12:15
12:20 "The role of Verification IP in Complex Core Design" by Saverio Fazzari from Cadence Design Systems (USA)


12:20 "Improving Design Timing and Simplicity for Lower Cost and High Performance Multistandard Audio Decoder STA012" by M. Bosco from STMicroelectronics (Italy) & S. Bordbar & S. Tiralongo from Synopsys (Italy)
12:25 12:25
12:30 12:30
12:35 12:35










12:40 LUNCH









12:40 LUNCH
12:45 12:45
12:50 12:50
12:55 12:55
13:00 13:00
13:05 13:05
13:10 13:10
13:15 13:15
13:20 13:20
13:25 13:25




13:30 "IP qualification : the user camp versus the tool and IP vendor camp"

organized by Philippe Magarshack, ST Microelectronics (France) with the participation of Alcatel (France), Philips (The Netherlands), ST Microelectronics (France) in the user camp and ARM (UK), Mentor Graphics (USA), Synopsys (USA), Verisity (USA) in the tool and IP provider camp




13:30 "Hardware/Software Partitioning Methodology for Systems on Chip (SoCs) with RISC Host and Configurable Microprocessors " by S. Takagi, At. Masuda & R. Ohyama from Toshiba (Japan), H. Eichel from Toshiba Electronics Europe (Germany) & N. Matsumoto, Toshiba (Japan)
13:35 13:35
13:40 13:40
13:45 13:45
13:50 13:50 "Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning" by H. Menager from Philips semiconductors (USA), M. Basel from Mentor Graphics (USA) & R. Kadiyala from Philips semiconductors (USA)
13:55 13:55
14:00 14:00
14:05 14:05
14:10 14:10 "Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often " by H. Sanghavi, Tensilica (USA) & S. Leibson from Tensilica (USA)
14:15 14:15
14:20 14:20
14:25 14:25
14:30 14:30 "A Framework for Selection of Cache Configurations for Low Power" by Z. Stamenkovic, F. Vater & Z. Dyka from IHP GmbH (Germany)
14:35 14:35
14:40 14:40
14:45 14:45
14:50

14:50 BREAK
14:55 14:55
15:00


15:00 "CoreWare® Subsystem based design" by B. Singh from LSI Logic Corporation (USA)
15:05 15:05
15:10 15:10
15:15 15:15 "Chip level IP for Low power Single chip Wireless Transceivers" by C. Faulkner from Jennic (UK)
15:20 15:20
15:25 15:25



15:30 BREAK
 15:30 "Methodology for flow integrations in a SOC design " by P. Guruswamy from Wipro (India) & H. Kwan from Texas Instruments (USA)
15:35 15:35
15:40 15:40
15:45 "Variable-integration-time image sensor for wide dynamic range" by Takaya Yasuda from Tokyo University of Science(Japan) Takaya Yasuda, Takahiro Ogi & Takayuki Hamamoto from Tokyo University of Science (Japan) & Kiyoharu Aizawa from University of Tokyo (Japan) 15:45
 "System Design Methodologies for System-on-Chip and Embedded Systems" by E. Blokken , J. Vounckx, J. Bormans, S. Vernalde & P. Wambacq from IMEC
15:50 15:50
15:55 15:55
16:00 16:00 "An analysis and implementation of high fairness arbitration mechanism by using level-table and static priority orders in shared bus architecture " by J. Suh & H.-J. Yoo from Korea Advanced Institute of Science and Technolgy
16:05 "Real-Time Face Detection Using Six-Segmented Rectangular Filter (SSR Filter) " by O. Sawettanusorn, Y. Senda & H. Yamauchi from Ritsumeikan University (Japan) 16:05
16:10 16:10
16:15 16:15 "Reliability-based Characterization of Semiconductor IP in SoC Design" by You-Pang Wei & Bill Wasserman from Legend Design Technology, Inc. (USA)
16:20 16:20
16:25 "Scalable IP Core of Vector Stream Cipher" by K. Umeno from Communications Research Laboratory and Chaos Ware Inc. (Japan) 16:25
16:30

16:30 BREAK
16:35 16:35
16:40 16:40
16:45 "Reconfigurable Processor Device from IPFlex Inc." by T. Sato from IPFlex Inc. (Japan) 16:45
 "Lessons learnt in IP Reuse " by C.Gendarme, F.Kleitz & I.Hrynchyshyn from Alcatel (France, Belgium), L.Ghanmi, M.Hamdoun & B.Missaoui from Design and Reuse (France), K.Benseffaj, A.Hanczakowski & M.Vandendriessche from STMicroelectronics (France) & M.Sarlotte & S.Gilles from Thales (France)
16:50 16:50
16:55 16:55
17:00 17:00


17:05 BREAK 17:05 "VSI Alliance Quality IP Metric " by K. Werner from Mentor Graphics (USA)
17:10 17:10
17:15 "A Low-Power 16-channel AD Converter and Digital Processor ASIC" by R.Esteve-Bosch, B.Mota, L.Musa & A.Jimenez-de-Parga from CERN & D.Subiela, S.Engels & L.Dugoujon from STMicroelectronics
17:15
17:20 17:20
17:25 17:25 "IP Core-centric ommunications protocol" by F. Seigneret from Texas Instruments (France) & OCP-IP Specification Working Group
17:30 17:30
17:35 "IP Cores for Accelerating JPEG2000 " by O. Cantineau from Barco Silex (Belgium)
 17:35
17:40 17:40
17:45 17:45
 "IP business models: A focus on IP quality and its impact"
organized by P.Dworsky, Synopsys (Director of Marketing, DesignWare IP) (USA) with the participation of T. Daniels, LSI Logic (Director, ASIC Technical Marketing), M. Evans, ARM (Director of IP Licensing) P. Hirt, ST (IP Procurement Manager) & J. Tully, Gartner/Dataquest (VP and Chief of Research)
17:50 17:50
17:55 "Creating High performance Resuable 10Gigabit ethernet MACs " by J. Balachandran from IMEC (Belgium), K. Jain & A. Kudale from GDA Technologies (India) & A. Saxena from GDA Technologies (USA)
17:55
18:00 18:00
18:05 18:05
18:10 18:10
18:15 "IP Core of Statistical Test Suite of FIPS PUB 140-2" by A. Hasegawa & S.-J. Kim from Communications Research Laboratory (Japan) & K. Umeno from Communications Research Laboratory and Chaos Ware Inc. (Japan) 18:15
18:20 18:20
18:25 18:25
18:30 18:30

18:35   18:35

18:40   18:40

18:45   18:45

18:50
18:50

18:55
18:55



19:00



19:05

19:00 BANQUET
19:00 BANQUET

DAY 2: November 14, 2003


Room1



Room 2
Session Time
 Paper Session Time
 Paper






8:00
 "Store and Forward Fat-Tree Architecture for on-Chip Networks" by Filippo Mondinelli from University of Brescia (Italy)
 8:00 "The CREC Reconfigurable Computer" by O. Cret from Technical University of Cluj-Napoca (Romania)
8:05 8:05
8:10 8:10
8:15 8:15
8:20 "SBAG : The on-chip STBus traffic analyzer" by Bernard Ramanadin from STMicroelectronics (France)
 8:20 "3+ Ways to Design Reconfigurable Algorithm Accelerator IP Block " by Tapio Ristimäki from Tampere University Of Technology / Institute of Digital and Computer Systems (Finland)
8:25 8:25
8:30 8:30
8:35 8:35
8:40 "CCP: Customizable Control Processor" by Gordon Fairley, IBM(Switzerland)


 8:40 "FPGA Coprocessors: Hardware IP for Software Engineers" by Robert Cottrel from Altera (UK)
8:45 8:45
8:50 8:50
8:55 8:55
9:00 "Spirit Compliant Platform Design using an IP Repository" by Mark Peryer from Mentor Graphics (UK)





















9:00
 "Configurable Processors and Reconfigurable Logic: Flexible Architectures for SOCs"

organized by Steve Leibson, Tensilica (USA) with the participation of IBM Research Lab (Switzerland), DAFCA (Design Automation for Flexible Chip Architectures) (USA), Laboratoire LIRRM (France), Analyst and editors from Gilder Technology, MicroDesign Resource, Gartner Research (UK)








9:05 9:05
9:10 9:10
9:15 9:15
9:20 "An ASIC Platform Manager" by G.Saucier, K.Skiba, Ph.Rols & Ph.Coeurdevey from Design And Reuse (France) & H.N. Nguyen from METASymbiose S.A. (France)
 9:20
9:25 9:25
9:30 9:30
9:35 9:35
9:40 "Structured ASIC Based SoC Design" by Rick Mosher from AMI Semiconductor (USA)

 		9:40
9:45 9:45
9:50 9:50
9:55 9:55
10:00 "ASIC platform: The key for successful IP based SOC design: Core based or interconnect based or technology structured?" organized by Tim Daniels, LSI Logic (UK) with the participation of :
Bus - Drew Wingard, Sonics (defending the bus)
IP - Ralph von Vignau or Chris Lennard, Spirit (defending Stds & IP)
Tech - Pat Mead, Altera (defending technology)
Tech - Balraj Singh, LSI Logic (defending IP & technology)
 		10:00
10:05 10:05
10:10 10:10
10:15 10:15
10:20 10:20
10:25 10:25
10:30 10:30
10:35 10:35
10:40 10:40
10:45 10:45
10:50
10:50
 COFFEE BREAK
10:55 10:55
11:00 11:00
11:05 11:05
11:10 11:10 "An IP Based Design Flow with ASIPs for the Design and Implementation of Digital Filters" by Sven Simon from Hochschule Bremen (Germany)
11:15 11:15
11:20 11:20
11:25 11:25
11:30 11:30 "Low-power Motion Estimation IP for MPEG-4" by Hongkyu Choi from Yonsei Univ. EE. (Republic of Korea)



11:35 COFFEE BREAK
 11:35
11:40 11:40
11:45 11:45

11:50 "A Fast SystemC Simulation Methodology for Multi-level IP/SoC Design " by Samy Meftali from LIFL (France)
 11:50
 Application of SoC in 4G Mobile Telephony Baseband Chip" by Rohan Sarker from Reliance Industries Limited (India)
11:55 11:55
12:00 12:00
12:05 12:05
12:10 "IP-Based SOC Design in a in-house C-based design methodology" by Marcello Lajolo from NEC (USA)
 12:10 "Design of a SoC for Low cost IC Testing" by Liakot Ali from Universiti Putra Malaysia (Malaysia)
12:15 12:15
12:20 12:20
12:25 12:25
12:30 "Architectural Exploration of Low-Power CORDIC Engine using Transaction-Level Models " by W. Cheng, P. Wu, L. Mastroleon from Stanford University (USA) and M. Hakansson from CoWare (USA) 12:30 "Concepts and implementation of the Philips Network-on-Chip " by John Dielissen from Philips
12:35 12:35
12:40 12:40
12:45 12:45









12:50



LUNCH
12:50
 LUNCH
12:55 12:55
13:00 13:00
13:05 13:05
13:10 13:10
13:15 13:15
13:20 13:20
13:25 13:25

13:30 "SoC Integration of Programmable Cores " by A. Wieferink & T. Kogel from RWTH Aachen (Germany) & A. Hoffmann, O. Zerres & A. Nohl from CoWare Inc. (USA)


13:30 "IP Based System Design for Aerospace and Military - The Time is now" by P. Southard from PDS Consulting, LLC (USA) & T. Ivey from MTI (USA)
13:35 13:35
13:40 13:40
13:45 "Architectural Analysis For A Multiprocessor SoC Using SystemC" by Mallik Moturi from Hughes Network Systems (USA)
 13:45
 "Performance: The Future of Embedded Processing " by Tom Petersen from MIPS Technologies, Inc. (USA)
13:50 13:50
13:55 13:55
14:00 "Transactional level as the new design and verification abstraction above RTL" by Bart Vanthournout from CoWare (Belgium)

 14:00 "An IP Based SoC Design – Reduces System Design Time" by Kiran Patel from Silicon Interfaces Pvt Ltd (India)
14:05 14:05
14:10 14:10



14:15
COFFEE BREAK

 14:15 "System for Active Design Knowledge Preservation and Reuse" by Chia-Huei Lee from Springsoft / Novas (Taiwan)
14:20 14:20
14:25 14:25
14:30 "SystemC in Harmony, not in conflict with RTL"

Organized by : Guido Arnout, CoWare chairman and OSCI president with the participation of
- Mark Burton, ARM Ltd.
- Ted Vucurevich,Cadence Design Systems, Inc.
- Frank Ghenassia, ST
- John Aynsley, Doulos 		14:30 "Sophocles: Cyber-Enterprise for System-On-Chip Distributed Simulation -- Model Unification"  by Pierre Boulet from LIFL (France)
14:35 14:35
14:40 14:40
14:45 14:45
 "Muti Chip, Multi Environment Simulation. Bringing Software closer to Hardware and saving $$" by Swaminathan Venkatesan from Wipro Technologies (India)
14:50 14:50
14:55 14:55
15:00 15:00 "Dead Horse or Sleeping Beauty – Will Embedded FPGAs Have a Role in Future SoC-Designs?" by Thomas Niedermeier from Infineon Technologies (Germany)
15:05 15:05
15:10 15:10
15:15 15:15 "Benefits of Reconfigurable IP in the Back-end SoC Development Process" by K. Lamb and T. Stansfield from Elixent Ltd (UK)
15:20 15:20
15:25 15:25
15:30 15:30 "New architecture for Configurable blocks using Differential" by Manjunath R & Gurumurthy from UVCE (India)
15:35 15:35
15:40 15:40
15:45
15:45
15:50
15:50
15:55
15:55
16:00
16:00
16:05
16:05
16:10
16:10
16:15
16:15
16:20
16:20
16:25
16:25
16:30
16:30

16:35

16:35

16:40

16:40