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Keynote Talks

• "IP Market Challenges: Today and the Next Generation " by John Chilton, Synopsys (USA)
• "Building Successful IP Partnerships - Selecting IP for Successful SoC Design" by Michael Kaskowitz, Mentor Graphics (USA)
• "IP Management in a Large Company" by Thierry Pfirsch, Alcatel (France)
• "IP Market Overview and Outlook" by Jim Tully, Gartner Dataquest (UK)

• "Meeting the challenges of 90nm SoC design" by Tim Daniels, LSI Logic (UK)
• "Infrastructure IP: Aiding SOC Yields " by  Yervant Zorian, Virage Logic Corp. (USA)
• "Creating good IP for physical design" by Paul Rodman, ReShape, Inc.(USA)

• " IP Transfer: a mapping problem " by Gabriele Saucier,  Design And  Reuse (France); Thierry Pfirsch, Alcatel (France); Menno ten Have,  Philips (Germany); Martin Radetzki, sci-worx  (Germany)
• " Collaboration Support in Design - What is the message from CSCW and Knowledge Co-Production?" by Konrad Kloeckner, Fraunhofer Institute for Applied Information  Technology (FHG-FIT) (Germany)
• " IP Configuration Management with Abstract Parameterizations " by Holger Lange, Martin Radetzki, sci-worx (Germany)

• "A powerful dual-mode IP core for 802.11a/b Wireless LAN" by Michel Eftimakis, NewLogic Technologies AG (France)
• "A Bluetooth radio in 0.18um CMOS" by  Paul van Zeijl, Ericsson Technology Licensing (Netherlands)
• "Optimizing MPEG-4 Video Decode on SH-5" by Antony Bowers and Benedict R. Gaster, SuperH (UK)
• "Design of an IP for a G729 voice decoding circuit " by  F. Sayadi,E. Casseau, M. Marzougui, M. Atri, R. Tourki,  E. Martin, Laboratoire d'EµE- Faculté des sciences de Monastir  (Tunisie); Laboratoire L.E.S.T.E.R - Université de Bretagne Sud (Lorien)
• "Bluetooth Baseband IP in an ARM9 environment " by Jeff Robertson, Ericsson Technology Licensing (Sweden)
• "Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA   Architecture for High Channel-Density VOIP Line Echo Cancellation" by Chang Choo, Silicon DSP (USA)
• "Efficient Free-to-Air DVB-T System Solution Supported by IP-Based  SoC Designs " by David McBrien, Imagination Technologies & Frontier Silicon (UK)
• "An Efficient FFT co-module using SOC approach " by Ali Ahmadinia, Shaahin Hessabi, Sharif University of Technology  (Iran)
  

• "IP Modeling and Reuse for SoC Design Using  Standard Bus " by  Imed Moussa and Thierry Roudier, TNI-Valiosys (France)
• "Tuning Fork - A Tool For Optimizing Parallel Configurable Processors" by Shay Gal-On, Steve Novack, Oz Levia, Improv Systems (USA)
• "Synthesizable Analog IP " by Navraj Nandra, Barcelona Design Inc. (USA)
• "ParaGraph - Shrinking the Parameter Space of IP utilizing Parameter Domains " by Vasco Jerinic, Dietmar Mueller, Chemnitz University of Technology (Germany)
• "IP Design for Dynamically Reconfigurable SoCs " by Tobias Oppold, Wolfgang Rosenstiel, University of Tuebingen  (Germany)
• "An Integrated Formal Approach for System on Chip " by Kong Woei Susanto, University of Glasgow (UK)

• "Synthesisable Verification IP " by David Murray, Duolog Technologies (Ireland)
• "Maximizing Verification Productivity: eVC Reuse Methodology (eRM)" by Andrey Shvartz, Verisity Design (France)
• "Attacking the Verification Challenges: Applying Next Generation Verification IP to Bus Protocol-based Designs" by Richard Pugh, Neill Mullinger, Jay Hopkins, Synopsys Inc, (USA)
• "Assertion Based Emulation Methodology" by Steve Wang, Axis Systems (USA)
• "Domain Verification Components (DVCs) for CoreInterconnect" by Janick Bergeron, Stephane Brefort, Andy Betts, Qualis Europe SARL (France)
• "Authoring Assertion IP using OpenVera Assertion Language" by Surrendra Dudani, Eduard Cerny, Synopsys, Inc. (USA)

• "Intellectual Property Reuse - A New Business Model" by Phil Rose, Cadence Design Foundry (UK)
• "Defining IP Mall Business Models and Processes for Taiwan's National Si-Soft Project" by Professor Charles V. Trappey, Professor Kuei Ann (Stella) Wen,  National Chiao Tung University; Professor Amy C. Trappey, National Tsing Hua University; Rayon Hsu, Avectec.com, Inc. (Taiwan)
• " Rights Management for FPGA Intellectual Property" by Tom Kean, Algotronix (UK)

• "Reduce SOC simulation and development time by designing with processors, not gates " by Steven Leibson, Tensilica Inc. (USA)
• "CASE STUDY - Hands-on lessons from a legacy RT-level ATAPI IP Reuse " by Jin-Seok Hong, Goang-Seog Choi, Ki-Seon Cho, Ju-Seon Kim, Jum-Han Bae, Samsung Electronics (Korea)
• "Top-down SoC Design Methodology " by Emre Tuncer, Wolfgang Helftricht, Monterey Design Systems, Inc. (USA)
• " Enforcing Design Rules To Develop Reusable IP " by by Kanwar Pal Singh, Ramakrishna Ayyagari, Cadence Design Systems (India)

• "Atlantic: a high-performance datapath interface for SOPC Designs'" by Robert Cottrell, Altera (UK)
• "Solving SOC Shared Memory Resource Challenges " by  W. David Schwaderer,Philippe Martin, Sonics Inc. (USA)
• "Deterministic and Balanced Architecture - VII-Pro " by Antolin Agatep, Jean-Louis Brelet, Xilinx, Inc. (USA)

• "Co-simulation and Communication Synthesis for Intellectual Properties IPs Based SOCs: Approach and Experimentation " by M. Marzougui, M. Abid, R. Tourki, Electronic and Micro-Electronic aboratory. Monastir (Tunisia); A. Baganne , LESTER Laboratory. U.B.S (Lorient France)
• "System-level Exploration of Queuing Management Schemes for Input Queue Packet Switches" by Chen He, University of Texas at Austin (USA); Marcello Lajolo, NEC USA, C&C Research Labs (USA); Margarida Jacome, University of Texas at Austin (USA)
• "Software Rich Chips " by Paul McLellan, VAST Systems Technology (USA)
• "Exchange of hardware dependent software IPs" by Patrick Blouet, ST Microelectronics (France); Gabriele Saucier, Lassaad Ghanmi, Karima Skiba, Design And Reuse (France)

• "Reusable Verification Infrastructure for a Processor Platform to deliver fast SOC development " by Stephen Brain, Glenn Farrall, Richard Tuck, Infineon Technologies (UK); Kambiz Khalilian, Infineon Technologies (USA)
• "Reusability and modularity in SoC Verification environment " by Achutha Jois, Vishal Dalal, Sasken communication Technologies Ltd. (India)
• "IP "Reuse Hardening" via Embedded Sugar Assertions" by Erich Marschner, Grant Martin , Cadence Design Systems (USA)
• "The Role of Functional Coverage in Verifying the C166S IP" by  Andrew Betts, Fabian Delguste, Stephane Brefort, Celia Clause,  Qualis (France); Angeles Salas, Thomas Langswert, Infineon
• "The SW replicate: Market estimation of a newcoming EDA segment" by Marco Pavesi, Italtel (Italy)

• "Bump in the Wire - An Ethernet Security Development Platform" by Doug Chisholm, Cadence Design Foundry (UK)
• "The role of sockets in platform based design: a case study of the OMAP platform" by Pete Cumming, Franck Seigneret, Texas Instruments (France)
• "IP-Reuse and Platform based designs " by Ramesh Chandra, STMicroelectronics, Inc. (USA)
• "The Configurable VLIW Processor As The Base For A Cost Effective SoC Platform " by Victor Berman, Improv Systems (USA)
• "Platform Based Design - Enabling fast SoC time to Market " by Juergen Hilsberg, IBM Technology Group (Switzerland)

• "FPGA to ASIC Strategy for Communication SoC Designs " by Rick Mosher, AMI Semiconductors (USA)
• "An IP-based SOC Design Kit for Rapid Time-to-Market " by Dr Robert Deaves, Dr Andrew Jones, SuperH (UK)
• "DAvE - Software based system evaluation in the pre-silicon phase " by Timo Bierbaum, Infineon technologies (Germany)
• "Object-Oriented Synthesis, Modelling and Partioning for SoC Design " by M. Winterholer, C. Schulz-Key, T. Kuhn, W. Rosenstiel, University of Tuebingen ( Germany)

• "Design-for-Test for SoC - Is there a fork in the roadmap? " by Ron Press, Mentor Graphics (USA); Richard Illman, Cadence Design Foundry (UK)
• "An Embedded Processor Architecture with extensive support for SOC debug " by Richard Curnow, Mark Hill, Andrew Jones, SuperH (UK)
• "Behavior Analysis for SoC Debugging " by Scott Sandler, Yu-Chin Hsu, George Bakewell, Bassam Tabbara, Novas Software (USA)
• "Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO " by  Andre Schneider, Karl-Heinz Diener, Günter Elst - Fraunhofer Institute for Integrated Circuits (Germany); Eero Ivask, Jaan Raik, Raimund Ubar - Tallinn Technical University (Estonia)

• "IP Exchange Activities and IP Needs for Japanese Electronics Market " by Motoaki Ito, Nobuyuki Miyazaki and Shojiro Mori, IPTC Corporation (Japan)
• "Activities of SIPAC in IP/SoC industry of Korea " by  Shiho Kim, SIPAC (Korea)
• "Si-Soft: A national research program for IP/SoC Design Promotion " by  Prof. Chen-Yi Lee, CIC (Taiwan)

• " External Memory Interfaces: Delivering Bandwidth to Silicon" by Alan Page, Denali Software (UK)
• "Proteo Interconnect IPs for Networks-on-Chip" by Ilkka Saastamoinen, Mikko Alho, Juha Pirttimäki, Jari Nurmi, Tampere University of Technology (Finland)
• "Models for Communication Tradeoffs on Systems-on-Chip" by Cesar A. Zeferino, Márcio E. Kreutz, Luigi Carro, Altamiro A. Susin, UFRGS (Brazil)
• "Design of communication interface based on configuration for  system on chip" by Issam MAALEJ, Guy GOGNIAT, Mohamed ABID, Jean Luc PHILIPPE,  Ecole Nationale d'Ingenieurs de Sfax (Tunisie); L.E.S.T.E.R.,  Université de Bretagne Sud (France)
• "A coherent mixed-signal verification environment based on Matlab " by Pat Overs, Cambridge Consultants Ltd (UK)

• "Tools and Methods for IP " by Ralf Seepold, FZI (Germany)
• "Experiences in Formal Checking of a DSP IP Core " by Nguyen H.N., Koumou P., Bull S.A.,METASymbiose S.A. (France); Candaele B., Sarlotte M., Antoine C., Emeriau S., Thales Communications (France)
• "A next generation interconnect concept to design high performance SoC's " by Carsten Demuth , Infineon (Germany)

• "A Parallel TCP/IP Offloading Framework for a TCP/IP Offloading Implementation " by Juan M. Solá-Sloan, Isidoro Couvertier, Universidad de Puerto Rico Mayaguez Campus (Puerto Rico)
•  "Static RTL Analysis of Multi Clock Domain Designs " by Mark Langer, Steffen Rülke,Fraunhofer IIS Erlangen/Branch Lab DA, Dresden (Germany); Alexander Krebs, Frank Dresig,AMD Saxony Limited Liability Company & Co. KG, Dresden Design Center (Germany)