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About this Event... IP 08 (IP-Based System Design) will be the 17th edition of the working conference on hot topics in the design world, focusing for the past 7 years on IP-based SoC design and held in the well known Silicon and Alliance Nanometer Valley in the French Alps. Important Dates • Deadline for submission of paper summary: September 25, 2008 • Notification of acceptance: October 19, 2008 • Final version of the manuscript: November 9, 2008 • Working conference : December 3-4, 2008 Areas of interest: IP Best practice • Business models • IP Exchange, reuse practice and design for reuse • IP standards & reuse • Collaborative IP based design Design    • IP packaging for Integration • IP and system configurability • IP platform based design    • IP integration in NoC • DFM and process variability in IP design Quality and verification • IP / SoC quality assurance • IP / SoC prototyping • IP / SoC verification and virtual prototyping • IP / SOC transaction level modelling Paper Submission Procedure To present a paper during the conference a summary of at least 3 pages is required for any submission. You may also apply to present a seminar paper on the topics that will be announced shortly. You can submit an electronic version of your extended abstract in a Word or PDF format using the Online Submission Form IP 08 Best Prizes Each year, the IP/SoC Conference is proud to recognize the excellent, novel, innovative and highly practical design ideas that authors contribute. Excellence in design - whether it be within an IP block or a complete system continue to be the future of the IP/SoC industry. View the winners of the IP/07 Best Design Paper Awards Any question ? Please contact us at  Exhibition In addition to the IP 08 working conference, the attached exhibition gives you the opportunity to see the reality of a SoC connected world. The exhibition will allow you to meet the most advanced suppliers and see the latest products. Why should you exhibit? IP 08 provides a turnkey solution to companies wishing to gain face-to-face contact with key players in the IP arena. The table top exhibition involves a low outlay in terms of financial cost, time out of office and organisational responsibilities, and gives a high yield in terms of high quality sales leads and company promotion. IP 08 is a simple way of increasing the products and services you sell and getting your name in front of a highly technical, decision making audience. Exhibitors, book your space now.

Conference The following keynote and introductive talks are already planned: Keynote Talks • "Open Innovation Platform and IP" by Douglas Pattulo , European Director, TSMC • "IP Reuse leading the way of Enterprise level IP management" by David Yoon, Sr. Manager of IP Management, Cisco systems • "IP management platforms: A success story" by Gabriele Saucier, CEO, Design And Reuse • "SoC/IP Market Overview and Outlook" by Jim Tully, Vice President, Chief of Research Semiconductors, Gartner • "Feeding the Beasts: Optimized Shared Memory Solutions for MPSoCs" by Drew Wingard, CTO, Sonics • "Research programs and model of collaboration: the Silicon Sea belt program" by Eisaku Ohtsuru, R&D Managing Director , Fukuoka Industry, Science & Technology Foundation • "A Breakthrough in Design Reuse and Modification" by Kathryn Kranen, President and CEO, Jasper Design Automation Three tracks will respectively address: • The well recognized Panels . Are planned: - "SOC Configurability -- Balancing Manufacturing and R/D Costs" moderated by Jim Tully from Gartner with the participation of Ian Phillips from ARM, Philippe Magarshack from STMicroelectronics, Yakov Levy from MIPS Technologies, Dan Hillman from Transmeta, Syed Zahid AHMED from Menta/Lirmm - "Is TLM 2.0 Truly the Panacea for Interoperability?" moderated by Gabriele Saucier from Design And Reuse with the participation of Markus Willems from Synopsys, Yossi Veller from Mentor Graphics, Jack Donovan from XtremeEDA Corp. - "Easy Third-Party IP Integration - Fact or Fiction?" moderated by Jim Tully from Gartner with the participation of Xerxes Wania from Sidense, Gabriele Saucier from Design & Reuse, Ralph Morgan from Synopsys, Christophe Frey from ARM, Ange Aznar from Wipro NewLogic, Jack Browne from MIPS - "IP vision for FPGA : Do complex FPGA designs rely on the use of vendor-created and third-party IPs ?" moderated by Dick Selwood from Embedded Technology Journal with the participation of Francois Kleitz from Alcatel Lucent, Stuart Nisbet from Xilinx, Mark Dickinson from Altera, Tom Moore from Actel, Ralph Morgan from Synopsys, Gabriele Saucier from Design And Reuse - "QA of Design flow" moderated by Hein Van Der Wildt from Fenix Design Automation with the participation of Christoph Heer from Infineon, Nangate, Jo Borel from STMicroelectronics, Michel Tabusse from Satin IP Technologies - "When will the Virtual Software Platform hook up to the Virtual Hardware Platform ?" moderated by Pierre Bricaud from Synopsys with the participation of Markus Willems from Synopsys, Simon Davidmann from Imperas, Jakob Engblom from Virtutech, Loic Le Toumelin from Texas Instruments - "Addressing the challenges in Power Modelling at the ESL Level" moderated by Glenn Perry from Mentor Graphics with the participation of Jack Donovan from XtremeEDA, Andrea Battistella from ST-NXP-Wireless, Ian Phillips from ARM • New, visionary scientific seminars on key topics organized by gurus in the field, including invited state of the art academic presentations. Are already planned seminars on: - Network on Chip with presentations from Olivier Bringman (FZI), Antonio-Marcello Coppolla (ST microelectronics), Srinivasan Murali (iNoCs) - Tera-Scale Architectures with presentations from Huy Nam Nguyen (Bull S.A.S. / METASymbiose S.A.S.), Professor Alain Greiner (UPMC/Lip6), Sjoerd MEIJER, NXP/Philips medical/Thalès - Verification for Embedded Software IP with presentations from Thomas Schulz (Robert Bosch GmbH), Djones Lettnin (University of Tübingen), Markus Winterholer (Cadence) - IP for In-System Silicon Validation and Debug with presentations from Miron Abramovici (Dafca), Yervant Zorian (Virage Logic), Andrew Swain (ARM) - IP-XACT Users’ Group First European Meeting • Technical sessions discussing the issues to be solved in the IP-based system design arena. - Business Model - Configurable Systems - Forum Talks - FPGA Design - High Level Modeling (1) - High Level Modeling (2) - IP Design (1) - IP Design (2) - IP Design (3) - IP Quality - NoC & SoC - Prototyping (1) - Prototyping (2) - SoC Design and Reuse (1) - SoC Design and Reuse (2) - Standard & Integration - Technology Impact (1) - Technology Impact (2) - Verification (1) - Verification (2) - Verification (3) -