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DAY 1: December 5, 2007
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AUDITORIUM
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07:00 |
Registration
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08:15 |
Welcome
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08:30 |
Keynote Talk: State of the Art in Patent Licensing Support
 By Mike McLean
Vice President of IPinsights
Semiconductor Insights
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09:00 |
Keynote Talk: Achieving Maximum Reuse Leverage: Lessons from benchmarking 1000+ IC projects
 By Ron Collett
President and CEO
Numetrics Management Systems, Inc.
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09:45 |
Which
IP Business and what Star IPs for the future?
Keynote Talk: Emerging Opportunities for Semiconductor IP
 By Jack Browne
VP of Marketing
MIPS Technologies
Keynote Talk: Next Chapter in IP: Enabling Innovation
 By Gagan Gupta
Senior Director of Product Marketing
ARC International
Panel: The future of IP industry. Are CPUs the only Stars in IP?
Moderator:
 Richard Wallace
Editor-in-Chief
EE Times
Panelists:
- Jack Browne, MIPS
- Gagan Gupta, ARC
- Haydn Povey, ARM
- Jeroen Leijten, Silicon Hive
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11:25 |
Break
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11:40 |
Keynote Talk: The Semiconductor IP Market
 By Jim Tully
Vice President, Chief of Research Semiconductors
Gartner
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12:10 |
Keynote Talk: IP website as a catalyst of IP industry
 By Gabrièle Saucier
CEO
Design and Reuse
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12:30
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Lunch
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AUDITORIUM
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ROOM
1
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ROOM
2 Design
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ROOM
3 High
Level
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13:30 |
Panel: A decade in standard based IP and what's the future for the next decade
Moderator:
 Joachim Kunkel
VP and General Manager
Synopsys
Panelists:
- Peter Hirt, IP Procurement and IP Partnerships Manager, ST Microelectronics
- Thierry Pfirsch, Alcatel Lucent
- Alex Haggenmiller, Infineon
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13:30 |
Session: IP business model
Chairman: William D. Billowitch (Cadence Design Systems)
-"IP Monetization: Your technology or your patents" by Mike McLean from Semiconductor Insights
-"The Gaisler Research Open-Source Business Model" by Per Danielsson from Gaisler Research
-"ESA IP Cores Service" by Kostas Marinis & Agustin Fernandez-Leon from ESTEC/ESA
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13:30
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Session: IP design 1
Chairman: Paolo Pezzati (Cadence)
-"FPGA based Complex System Designs: Methodology and Techniques" by Kodavalla Vijay Kumar from Wipro Technologies
-"A FPGA-based solution for enforcing dependability and timeliness in CAN" by José Rufino from FCUL, Ricardo Pinto & Carlos Almeida from IST-UTL
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13:30
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Session: TLM & System C Modeling
Chairman: Laurent Ducousso (STMicroelectronics)
-"Reducing IPCore Design Time Using Behavioral Synthesis and Synthesizable TLM Communication: an MPEG-2 Case Study" by Cirdes Borges, Marcelo Lucena, Vinicius Kursancew, Vítor Schwambach & Edna Barros from UFPE
-"Adapter Based Distributed Simulation of Multiprocessor SoCs Using SystemC" by Aravinda Thimmapuram from NXP Semiconductors
-"Accelerating SoC Design using SysML and SystemC1" by Waseem Raslan from Mentor Graphic Egypt & Ahmed Sameh from The American University in Cairo
-"SystemC Mixed-HDL IP Reuse Methodology" by Rudra Mukherjee, Gaurav-Kumar Verma & Arnab Saha from Mentor Graphics
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14:30
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Break
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14:30
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Break
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14:45
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Session: IP management, delivery and Exchange
Chairman: Francois Kleitz (Alcatel)
-"Collaborative engineering approach towards IP-based SoC design" by Adam Pawlak, Piotr Penkala & Pawel Fras from Silesian University of Technology, Havard Jorgensen from AKM AS & Wojciech Sakowski from Evatronix SA
-"IP Tagging and Tracing in IP centric Design, Project and Product management" by Gabrièle Saucier & Philippe Ozil from Design And Reuse
-"A SEMIAUTOMATIC IP DISTRIBUTION TOOL" by Millena Gomes, Cristiano Araujo, Felype Santiago & Edna Barros from UFPE
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14:45 |
Break |
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14:50
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Keynote Talk: A decade in Library IP and Mixed Analog IPs
 By Mike Murray
General Manager of Mixed Signal IP
Silicon & Software Systems (S3)
Panel: A Decade in Library IP and Mixed Analog IPs
Moderator:
 Bob Tait
Marketing Director of Consumer Silicon
Silicon & Software Systems (S3)
Panelists:
- Jean-luc Pelloie, Director SOI Technology, ARM
- Jean-François Pollet, Chief Innovation Officer, Dolphin Integration
- Sergio Kusevitzky, Vice-President of Marketing - Chipidea Analog Group, MIPS Technologies
- Navraj Nandra, Director, Product Marketing Mixed-Signal IP, Synopsys
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14:50 |
Break |
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15:15
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Session: IP design 2
Chairman: Paolo Pezzati (Cadence)
-"Performance Enhancements in System Packet Interface (SPI) 4.2 IP Core" by Kaushal Buch, Tarang Popat & Rahul Jain from eInfochips Ltd
-"Transmitter/Receiver IP cores for MIPI Camera Serial Interface 2(CSI-2) and D-PHY" by Soon Kwon, Eugin Hyun, Yong-Hwan Lee, Jong-Hun Lee & Woo-Young Jung from DGIST
-"Dual Mode SMIA/MIPI Receiver Supporting 2Gbps" by Yoav Lavi from VLSI Plus
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15:20 |
Session: High level modeling
Chairman: Bernard Courtois (IMAG)
-"Modelling Embedded Systems at Functional Untimed Application Level" by Sandro Penolazzi, Ahmed Hemani & Mohammad Badawi from KTH
-"Rapid Creation of Application Models from Bandwidth Aware Core Graphs" by Joao Otero from NEC Laboratories America, Francesco Regazzoni from ALaRI & Marcello Lajolo from NEC Laboratories America
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15:45
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Break |
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16:00
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Session: IP integration and standards
Chairman: Ian Mackintosh (OCP IP)
-"A Chip IP Integrator for System Level Design" by Mikhail Baklashov from ARM, Inc.
-"Generic Driver Model using hardware abstraction and standard APIs" by Amar Amar, Shirish Joshi & Don Wallwork from Cisco Systems Inc
-"SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker" by Jan Langer, Vasco Jerinic from Chemnitz University of Technology & Ulrich Heinkel from Chemnitz University of Technology, Frank Dresig from AMD Saxony LLC and Co. KG & Jan Langer
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16:00
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Break |
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16:10
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Break |
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16:30
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Panel: Open Source for Hardware Design
Moderator:
 Francois Kleitz
Alcatel Lucent
Panelists:
- Per Danielsson, Chief Executive Officer, Gaisler research
- Shrenik Mehta, Sr. Director, Frontend Technologies & OpenSPARC Program, Sun Microsystems
- Pierre Bricaud, Synopsys
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16:30
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Break
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16:30
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Panel: Is networking the solution for interconnect design closure?
Moderator:
 Srinivasan Murali
Ecole Polytechnique Federale de Lausanne
Panelists:
- John Bainbridge, Founder and Chief Technology Officer, Silistix
- Marcello Coppola, STMicroelectronics
- Philippe di Crescenzo, Product Marketing Director, Arteris
- Milos Krstic, IHP Microelectronics
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17:00
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Break |
17:00
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Session: IP design 3
Chairman: Jeroen Leijten (Silicon Hive)
-"AMASS Core: Associative Memory Array for Semantic Search" by Pal Rujan from LCI GmbH, Francois Vuillod & Benedikt Gomm from UniUlm & Marius Monton & David Castells from UAB
-"IP Core of On-line ICA Algorithm" by Song-Ju Kim from NiCT & Hideaki Terai & Ken Umeno from NiCT, ChaosWare Inc.
-"A 0.79-mm^2 29-mW Real-Time Face Detection IP Core" by Yuichi Hori & Tadahiro Kuroda from Keio University
-"H.264/AVC HDTV Motion Compensation Soft IP" by Bruno Zatt, Arnaldo Azevedo, Luciano Agostini, Altamiro Susin & Sergio Bampi from UFRGS
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17:30 |
Break |
17:30
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Session: IP encryption
Chairman: Mike Bursell (Certicom)
-"DesignTag: A Thermally Sensed Security Tag to Protect Chip Designs" by Tom Kean from Algotronix Ltd, David McLaren & Carol Marsh from Algotronix Ltd. and ISLI
-"Hardware Security Requirements for Embedded Encryption Key Storage" by Craig Rawlings from Kilopass Technology Inc. & Mike Bursell from Certicom
-"Cryptographic Hardware Implementation in an IP-based System-on-Chip (SoC)" by Illiasaak Ahmad, N. M. Thamrin & M Khalil-Hani from Universiti Teknologi Malaysia
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17:45 |
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17:50
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Panel: Semiconductor IP – Who should be the Standards Torch Bearer ?
Moderator:
 Warren Savage
CEO
IPextreme
Panelists:
- Bill Martin, Mentor Graphics
- Victor Berman, Improv Systems
- Ian Mackintosh, OCP IP
- Pierre Bricaud, The SPIRIT Consortium
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17:50
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Exhibitor track [1]
Chairman: Bobby Behnam
-"Dassault Systèmes ENOVIA" by Felix Beniamine
-"Analog and Mixed-Signal design solutions for SoC makers" by Thierry Delmot from nSilition
-"Satin IP Technologies" by Michel Tabusse
-"A solution for Noise impact in Analog Mixed Signal SoC" by Brieuc Turluche (CWS)
-"LEON3 and the GRLIB IP-library" by Per Danielsson (Gaisler)
-"The AMASS Project: a general in-memory search platform for database, text, semantic web, and multimedia management applications" by Dr. Pal Rujan from LCI GmbH
-"VaST Systems Technology" by Jean-Marc TALBOT
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18:30
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18:30
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19:00
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19:00
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19:15 |
Banquet
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Join us at the D&R 10th Anniversary Party
for knowing more about French traditional food and wine from French
regions, sharing our birthday cake, enjoying music and our friendly
community ambiance . |
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DAY 2: December 6, 2007
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AUDITORIUM
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ROOM
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ROOM
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ROOM
3 |
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08:15 |
Panel: IP/SoC Prototyping
Moderator:
 Huy-Nam Nguyen
Head of System Modelling and Verification Service
Bull / METASymbiose
Panelists:
- Luc BURGUN, President and CEO, EVE
- Syed Zahid Ahmed, LIRMM / Menta
- Lars-Eric Lundgren, General Manager of Synplicity Hardware Platforms Group, Synplicity
- Eric Selosse, Mentor Graphics
- Helena Krupnova, STmicroelectronics
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08:15
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Exhibitor track [2]
-"Ultra-Low Power? Think Multi-ASIP SoC!" by Gert Goossens from Target Compiler Technologies
-"EVE" by Luc Burgun
-"Accelerating Product Development with IP Subsystems" by Rick Tomihiro from Mentor Graphics
-"What's missing? An efficient intranet IP Reuse infrastructure" by Gabriele Saucier from Design And Reuse
-"ASIC Prototyping with FPGAs" by Mike Dini from The Dini Group
-"A Formal Verification Process to Ensure Error-free IP" by Michael Siegel from OneSpin Solutions
-"Breaking the 10G Barrier" by Tony Pialis from Snowbush/Gennum
-"Ansoft" by Rémy Fernandes
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08:30
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Session: Verification I
Chairman: Lyes Benalycherif (STMicroelectronics)
-"Your Verification Methodology Ran Out of Steam and Your Project is Failing : How to Quickly Ramp Your Team and Apply the Latest Techniques to Tape Out Successfully" by Nick Heaton & Hamish Hendry from Cadence Design Systems, Inc.
-"A Comparison of Assertion Based Formal Verification with Coverage driven Constrained Random Simulation, Experience on a Legacy IP" by Jentil Jose & sachin Abdul Basheer from Wipro Technologies
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8:45
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Session: Power optimization 2
Chairman: Joseph Borel (JB-R&D)
-"Predictable, Automated Verification of Protocol Compliance : Methodology Guidelines and Best Practices for Achieving Compliance Closure" by Dimitry Pavlovski, Moshik Rubin & Liron Stoler from Cadence Design Systems, Inc.
-"Mixed Signal Drivers for Ultra Low Power and Very High Power Applications" by Offer Schwartsglass from Avnet ASIC Israel (AAI)
-"Accurate System Level Power Estimation through Fast Gate-Level Power Characterization" by Philippe Soulard & Sue Xu from NXP Semiconductors
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09:15
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Break
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09:30 |
Break
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09:30
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Session: Verification II
Chairman: Mark Hampton (Certess)
-"Re-Use of Unit level verification environment for verification of memory controller" by Aniruddha Baljekar from NXP Semiconductors
-"Case Study: Annotating OVL 2.0 with SVA Assertions" by Jiang Long, Andrew Seawright, Bipul Talukdar, Vibarajan Viswanathan & Kenneth Larsen from Mentor Graphics
-"SystemC: Key modeling concepts besides TLM to boost your simulation performance" by Martin Schnieringer from VaST Systems Technology
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09:45 |
Panel: Implementing Security of On-Chip Resources
Moderator:
Jim Tully
VP and chief of research for semiconductors
Gartner Dataquest
Panelists:
- Gagan Gupta, ARC International
- Steve Cliadakis, Sidense
- Mike Bursell, Certicom
- Semiconductor Foundry Representative
- Chip vendor with secure key storage requirement
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10:30 |
Break
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10:30
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Break
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10:30
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Break
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10:45 |
Break
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11:00 |
Panel: What’s needed to service the power conscious emerging mobile video marketplace?
Moderator:
 William Billowitch
Marketing Director, IP & EDA Alliances
Cadence
Panelists:
- Gagan Gupta, Director of Product Marketing, ARC
- Azzedine Boubguira, Dibcom
- Jack Browne, VP of Marketing, MIPS Technologies
- Jeroen Leijten, Silicon Hive
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11:00
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Open Forum: IP design methodology
Chairman: Ahmed Jerraya (CEA-LETI, MINATEC)
-"Software - the X factor" by Chris Turner from Cambridge Consultants
-"Timing annotation of UnTimed Functional models for architecture use-case" by Rajiv Gupta from HCL Technologies
-"Real-World Reuse: RTL Recycling" by Tom Dewey & Gordon Walker from Mentor Graphics Corp.
-"Auto SOC Top Design integration" by veena S Chakravarthi, Dinesh A & Kumar M N from Centillium India Pvt Ltd Bangalore & Gurumurthy K S from UVCE Bangalore
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11:00
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Session: Configurable platform
Chairman: Huy-Nam Nguyen (Bull / METASymbiose)
-"A configurable FPGA-based multi-channel high-definition Video Processing Platform" by Kambiz Khalilian from Omaha Microsystems & Bernd Merkl from Visual Communication Systems
-"A Configurable HW/SW Platform for Video Application" by ahmed ben atitallah from ENIS, Patrice Kadionik from IMS, Nouri Masmoudi from ENIS & Hervé Levi from IMS
-"Designing FPGA Based Reliable Systems Using VirtexTM-5 System Monitor" by Sanjay Kulkarni from Xilinx
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10:45 |
Session: Verification III
Chairman: Olivier Haller (STMicroelectronics)
-"Virtual Prototyping Environment for Multi-core SoC Hardware and Software Development" by Syed Abrar from NXP
-"Creating Interoperable and Reusable Verification IP in SystemVerilog with the Open Verification Methodology (OVM)" by John Rose & Dave Tokic from Cadence Design Systems, Inc. & Dennis Brophy from Mentor Graphics Corporation
-"Advanced techniques for IP design and verification" by Rangarajan Sundaravaradan & Vishwanath Balasubramanian from NXP Semiconductors
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12:00 |
Lunch
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12:45 |
Keynote Talk: Functional Verification of IP: Quo Vadis?
 By Dr. Wolfram Büttner
CTO
OneSpin Solutions
Panel: Highest Quality IP: Dream or Reality?
Moderator:
 Peggy Aycinena
Editor
EDA Confidential
Panelists:
- Eric Panu, R&D Group Director of Verification Methodology and VIP, Cadence
- Mark Hampton, CTO, Certess
- Olivier Haller, STMicroelectronics
- Steve Neill, Managing Director, Infineon UK ltd.
- Dr. Wolfram Büttner, CTO, OneSpin Solutions
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12:45
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Open Forum: IP best practice
Chairman: Antonio-Marcello COPPOLA
-"The PCIe IP Market consolidating. Is it necessarely the Commoditization of the PCIe IP?" by Eric ESTEVE
-"The good? The bad? The ugly? IP Perspectives from Vendor to SOC Designer" by Navraj Nandra from Synopsys, Inc, David Chiapinni from Matrox & Massimo Vanzi from Accent
-"Designing Around an Encrypted Netlist: Is The Pain Worth the Gain?" by Scott Barrick from Mentor Graphics
-"A Different Path to IP Success: A Decade-Plus Delivering Cores the CAST Way" by Hal Barbour from CAST, Inc.
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12:45
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Session: SoC design
Chairman: Bill Martin (Mentor Graphics)
-"Delivering compatible IP from Microcontrollers to Mobile Internet Platforms" by Shyam Sadasivan & Haydn Povey from ARM
-"A re-usable architecture for functional isolation of SOCs" by Andrew Jones & Stuart Ryan from STMicroelectronics
-"Improving design turn around time on a complex SoC by leveraging a reusable low power specification" by Herve Menager, Michel Korenhof & Michiel Huiskes from NXP Semiconductors
-"IPTV Development and the Hybrid Set-Top Box" by Keri Waters from Micronas USA
-"Automation in IP based SoC development: Case study of a media processor subsystem" by Haridas Vilakathara from NXP semiconductor
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12:45
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Session: NoC and interconnect
Chairman: S. Murali (EPFL)
-"Placement of different type nodes in a Network-on-chip graph" by Elena Suvorova & Yuriy Sheynin from Saint-Petersburg University of Aerospace Instrumentation
-"XB07: A Highly Reusable Crossbar Architecture for Multiprocessor System on Chip (MPSoC)" by Soeren Sonntag, Helmut Reinig, Stefan Linz, Frank Pitter & Martin Ruhwandl from Infineon Technologies
-"An HDTV SoC based on a mixed circuit-switched / NoC interconnect architecture (STBus/VSTNoC)" by Ignazio Urzi, Claire Bonnet, Philippe D'Audigier & Olivier Sauvage from ST Microlectronics
-"Performance verification methods developed for an HDTV Soc integrating a mixed circuit-switched / NoC interconnect (STBus/VSTNoC)" by Claire BONNET, Ignazio URZI, Philippe D'AUDIGIER & Olivier SAUVAGE from STMicroelectronics
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14:00
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Break
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14:00
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Break
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14:05
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Break |
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14:15
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Session: Analog mixed signal
Chairman: Kunihiko Tsuboi (STARC)
-"Designing High Quality Mixed-Signal IP at 65nm and below" by Dino Toffolon & Navraj Nandra from Synopsys
-"Mixed-Signal Verification for USB 2.0 Physical Layer IP" by Hany Bakeer, Omar Shaheen & Haitham Eissa from Mentor Graphics
-"UWB Time-interleaved ADC exploiting SAR" by Silvia Dondi, Marco Bigi, Andrea Boni & Matteo Tonelli from Silis s.r.l.
-"Design, Simulation and Testing of Switched-Capacitor Sigma–Delta ADC" by Gopan George, Sanju Gopal, Biju Oommen & Ravindra Kumar from Centre for Development of Advanced Computing
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14:15
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Session: Architectural synthesis
Chairman: Warren Savage (IPextreme)
-"USB Host IP-Core Hardware And Software Concurrent Development" by Adelmario Douglas from UFPE
-"A fully generic FEC generator for ASIC/FPGA" by Amir H. Farahani, Shahin Haghi Tabrizi, Mohammad Khalilzadeh & Jeyran Hezaveh
-"IPGenius, an on-line configurable IP Generator" by Iakovos Stamoulis, Polytimi Kolokytha, Theodore Roudas & George Sidiropoulos from Think Silicon Ltd
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14:25
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Open Forum: Test and simulation
Chairman: Hein van der Wildt (Fenix-DA)
-"Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Bring-up" by Pankaj Singh from Texas Instruments India (P) Ltd
-"Development and use of an Instruction Set Simulator of 68000-compatible processor core" by Filip Rak from Evatronix SA & Wojciech Sakowski from Silesian University of Technology
-"Preservation of Circuit Structure and Timing during Fault Emulation in FPGA" by Leos Kafka & Martin Danek from UTIA AV CR & Ondrej Novak from Czech Technical University in Prague
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14:30
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Break
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15:00
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Panel: Collaborative platform for Electronic Subsystem
Moderator:
 Bill Martin
General Manager, Intellectual Property Division
Mentor Graphics
Panelists:
- Peter Hirt, IP Procurement and IP Partnerships Manager, ST Microelectronics
- Jauher Zaidi, CEO Founder, Palmchip
- Kalar Rajendiran, Senior Director, Marketing, eSilicon
- Rick Tomihiro, Marketing Director, Silicon and Embedded SW IP, Mentor Graphics
- Bill Chown, SLED Product Group Director, Mentor Graphics
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15:15
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Break
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15:25 |
Break |
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15:30 |
Open Forum: Systolic and 2D array
-"Systolic FIR Filter IP Based FPGA" by Abdelhamid GOUGAM & Djamel Benazzouz from University of Boumerdes
-"An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs" by IMRAN-RAFIQ QUADRI, SAMY MEFTALI & JEAN-LUC DEKEYSER from LIFL, USTL, INRIA FUTURS
-"VLSI Based On Two-Dimensional Reconfigurable Array Of Processor Elements And Theirs Implementation Of Numerical Algorithms In Real-Time Systems" by Nick Lookin from Institute of Engineering Science, Vadim Bersenev from Urals Division of RAS & Michael Trapeznikoff from SPAA
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15:30
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Break
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15:30
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Session: Test bench and simulation
Chairman: H. Krupnova (STMicroelectronics)
-"eTBc: A Semi-Automatic Testbench Generation Tool" by Isaac Maia & Karina R. G. da Silva from LINCS/CETENE, Leandro Max, Romulo Camara & Elmar U. K. Melcher from Federal University from Campina Grande
-"Validation Approaches for a Product Family" by Leela Bhaskarabhotla, Mee Hing He & Anjali Vishwanath from Infineon Technologies Asia Pacific Pte Ltd,
-"Upfront Analysis of Low Power Specification, Assertions and Testbench to Enable Reuse" by Kanwar Singh from Cadence Design Systems
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15:45
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Session: Back end design
Chairman: D. Vellou (CEA/LETI)
-"Integration of Design-for-Analysis in IC Layout Design in meeting the Challenges of Shrinking Technology" by Khim-Hou Lee from Infineon Technologies
-"Enhanced Cross Coupled Low Noise Amplifiers" by Hossam Ali from silicon vision & Khalid Sharaf from Ain shams university
-"IP Gate Count Estimation Methodology during Micro-Architecture Phase" by Kodavalla Vijay Kumar from Wipro Technologies
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16:30 |
Cocktail
- BEST IP
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Join us for the Best IP Prizes Cocktail
and enjoy French Champagne ..
Au revoir and see you next Year |
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18:00
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