Temento Systems announces the release of DiaLite Platform Edition introducing PSL On Chip Verification (OCV)
A PSL Assertion Checker module is now available to enable At Speed properties verification, directly on the chip. Major features and improvements include PSL 1.1 language support, PSL IP automatic generation and insertion and PSL debug manager. This Edition takes advantage of the DiaLiteTM Instrumentation benefits and complex PSL functions can be associated with triggers IP cores. Combining the instrumentation IP cores on a same platform enlarge the debug possibilities like never done before.
PSL On Chip Verification (OCV) will allow designers to create PSL properties (A Boolean & temporal set of expressions describing system behaviour) that address their design checking requirements. Translation of PSL properties into VHDL/Verilog languages enable to generate IP Assertion Checker Verification Units (ACVU) which are then embedded into the user's design. The verification is performed directly on the chip and runs at design speed.
Another major benefit is offered with PSL incremental analysis capability which enable to progress in the debug without being obliged to do several synthesis loops. Bringing PSL High Level systems specifications on chip allows to detect critical bugs earlier and faster.
Working with assertions provides more information and can drastically improve the understanding of the internal behavior of the design. Implementing DiaLiteTM PSL Assertion Checker as part of the design process will create in any case a considerably higher quality of design and speed up time-to-market.
Pricing and Availability
Release 4.5 of DiaLiteTM Platform Edition is available now on Windows XP, 2000/NT and Solaris. Subscription licenses start from €15 000.
About Temento Systems
Temento Systems S.A. provides Electronic Design and Test Automation (EDTA) solutions that enable engineers to test and debug electronic products, including System on Chip (SoC), FPGAs, Boards, Multi-Chips Modules (MCMs) and Systems. Unlike traditional EDA software providers, Temento Systems offers a broad range of solutions focused on systems design test, starting from the earliest stage of design definition (virtual test), straight through hardware testing (physical test).
http://www.temento.com
The Temento Systems name and logo are trademarks of Temento Systems Corporation.
All other trademarks and service marks are the property of their respective owners.
|
Related News
- Temento Systems announces PSL On Chip Verification (OCV) in new DiaLite Edition & the Release 4.5
- Temento Systems announces the support of System Verilog Assertions among the new features of DiaLite Platform Edition and of TemStorage
- New Release of Cadence Incisive Platform Doubles Productivity of SoC Verification
- Temento Launches an Innovative Business Model for Its 'Dialite' Debug Platform
- Knowlent Ensures Analog Sign-Off With Latest Opal Verification Platform; New 4.0 Release Offers Testbench for Up-coming PCI Express Gen 2 Standard
Breaking News
- Arm revenues up 47%; shares fall
- Sondrel awarded new Video Processor ASIC design and supply contract for a leading provider of High-Performance Video systems
- X-Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ - a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core
- Softbank reported to be in talks to buy Graphcore
- VESA Elevates PC and Laptop HDR Display Performance with Updated DisplayHDR Specification
Most Popular
- Synopsys Enters Definitive Agreement to Sell its Software Integrity Business to Clearlake Capital and Francisco Partners
- Fabless semiconductor startup Mindgrove launches India's first indigenously designed commercial high-performance MCU chip
- sureCore announces successful tape-out of cryogenic IP demonstrator
- Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
- Announcing Availability of Silicon-Proven 12bit 1Msps SAR ADC IP Core for Whitebox Licensing with Royalty Free
E-mail This Article | Printer-Friendly Page |