German company to introduce PLL IP core at DAC
EE Times: German company to introduce PLL IP core at DAC | |
(06/10/2005 12:52 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=164302158 | |
SAN FRANCISCO Cologne Chip AG plans to introduce a new intellectual property (IP) core design Monday (June 13) at the Design Automation Conference (DAC) in Anaheim, Calif. The core design, C3-PLL-2, is a phase-locked loop (PLL) for frequency synthesizer applications, based on Cologne Chip's Digicc technology design approach. According to Cologne Chip (Cologne, Germany), the core is fully digital, designed for use with standard cell libraries for digital logic, independent of process technology and chip geometry and occupies a smaller silicon space than that of competing technologies. Cologne Chip said information about C3-PLL-2 pricing and availability could be obtained through the company's Web site.
| |
- - | |
Related News
- True Circuits Introduces New Synthesizable Precision PLL and Synthesizable Micro PLLs and DLLs and Demonstrates Silicon Proven DDR PHY
- True Circuits Showcases Revolutionary DDR 4/3 PHY and latest PLL and DLL Hard Macros at DAC
- Pulsic to Introduce Integrated, Full-chip Planning and Top-level Routing Solution for Custom IC Design at DAC 2011
- True Circuits Attends DAC, Features Complete Line of PLL and DLL IP
- Ezurio and Packetcraft Introduce Talking Sensor Rapid Prototyping Kit with Bluetooth Auracast Broadcast Audio Capability
Breaking News
- Arm revenues up 47%; shares fall
- Sondrel awarded new Video Processor ASIC design and supply contract for a leading provider of High-Performance Video systems
- X-Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ - a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core
- Softbank reported to be in talks to buy Graphcore
- VESA Elevates PC and Laptop HDR Display Performance with Updated DisplayHDR Specification
Most Popular
- Synopsys Enters Definitive Agreement to Sell its Software Integrity Business to Clearlake Capital and Francisco Partners
- Fabless semiconductor startup Mindgrove launches India's first indigenously designed commercial high-performance MCU chip
- sureCore announces successful tape-out of cryogenic IP demonstrator
- Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
- Announcing Availability of Silicon-Proven 12bit 1Msps SAR ADC IP Core for Whitebox Licensing with Royalty Free
E-mail This Article | Printer-Friendly Page |