Functionality
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Dataconverter (ADC & DAC) IP is sought in TSMC 0.13um process (preferrably logic process and upto 6 layers of metal)
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External compatibility and integration requirements
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IP is to be integrated inside a mixed-signal SOC. Integration support is mandatory such that the IP is fully integrated into customer's chosen design flow. Silicon proven designs are preferred.
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Timing or Performance requirements
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ADC & DAC sample rate is 80 MSPS. IP that is area and power optimized will be preferred. No 3.3V designs please - the IP must be based on a single 1.2V nominal supply. ADC input range must be 1Vpp (differential) and DAC output range should preferrably be 1Vpp (differential; this spec is somewhat flexible for the DAC)
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Technology Requirements
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TSMC 0.13um process (different process flavours are OK for now e.g. 6 versus 8 layers of metal or MIM caps versus no MIM caps etc.)
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Availability Timing
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Now
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Support requirement
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Integration support such that IP is fully integrated into the customer's chosen design flow. Some customization work may also need to be performed. Customer may ask for additional enhancements based on the specific application.
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Quality requirement
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Preference will be given to silicon proven designs.
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Business Scheme Requirement
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IP core will be licensed with the option to make changes/enhancements as deemed necessary by the customer. These improvements may be made directly by the customer with or without any help from the IP vendor.
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Other Constraints
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None
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