Tharas Systems introduces T-FORCE for Verification
On-demand, Subscription-based Program Leads Industry in Price and Capacity Flexibility
SANTA CLARA, Calif. — August 16, 2004 — Tharas Systems Inc. today announced Tharas Flexible On-demand Rental Collaborative Environment - T-FORCE (SM), an on-site subscription verification program. T-FORCE, with subscription rates starting at $10,000 per month, is the most cost-effective subscription program on the market for accelerated functional verification of complex ASIC and system designs.
T-FORCE, developed for customers with flexible verification needs, provides best-in-class accelerated verification at an affordable price. Projects with fluctuating verification capacity needs can increase or decrease hardware-assisted verification as necessary. The entry level of the program gives a customer the ability to verify up to 4-million gates.
Shrinking time-to-market window demands faster turn-around-time, higher throughput, enhanced debug environment, and ease-of-use comparable to that of software simulators. Purchasing hardware-assisted verification technology is a huge capital expense that carries the very real possibility of obsolescing that investment every other year. T-FORCE virtually eliminates the fiduciary concern with on-demand access to capacity and performance throughput at an affordable price. The on-site subscription model builds acquisition credits towards future purchases.
T-FORCE brings an industry-leading accelerated-verification solution based on Hammer 100 to the mainstream. The patented Hammer custom-processor architecture compiles Verilog, VHDL or mixed-language designs at 20-50 million RTL equivalent gates per hour on a single workstation – the fastest compilation time in the industry. The modular compiler enables design changes without full compile for even faster design preparation time. Hammer offers an advanced debug facility with concurrent, parallel and progressive waveform conversion to industry standard formats such as fast-signal database (FSDB), value-change dump (VCD), or VCD post-processing data (VPD).
"T-FORCE re-defines hardware-assisted verification by bringing the power of Hammer to rank and file engineers. Project managers may now subscribe to the best solution addressing their verification needs without the headaches of long-term obsolescence and expensive acquisitions," said Rahm Shastry, president and CEO of Tharas Systems.
"Time-to-market is the name of the game in the high-performance graphics market," said Narendra Konda, verification manager at nVIDIA Corporation. "nVIDIA often experiences a throughput crunch after initial bring-up. With T-FORCE, we acquired just the right amount of capacity for the initial bring-up of full-chip RTL while peak capacity needs were addressed by this innovative subscription program."
"At Raza Microelectronics, Inc. we watch our capital expense budget carefully. T-FORCE gave us access to the state-of-the-art, accelerated-verification technology at an affordable price. Tharas shared the risk during our mission-critical project," said Atiq Raza, chairman and CEO, Raza Microelectronics.
"We evaluated several competing hardware-accelerated solutions," commented Anoop Khurana, vice president of engineering at Ikanos Communications. "However, we were concerned about acquiring a solution that may become obsolete within a year. T-FORCE is the most affordable subscription program that met our acceleration expectations. We were able to quickly switch to a Hammer verification flow in just one week."
Pricing and Product Availability
T-FORCE pricing depends on user configuration and commitment duration. The list price starts at $10,000 per month for verification capacity up to 4-million gates. For more information on product pricing and availability call Tharas Systems in North America at 1.408.855.3200. For pricing and availability outside of North America visit http://www.tharas.com/contact.
About Tharas Systems
Founded in 1998, Tharas Systems is privately held with corporate headquarters located at 2518 Mission College Blvd., Suite 101, Santa Clara, CA 95054. Its high-performance verification technology leads to significant shortening of the verification cycle and material reduction in time-to-market for designers of complex integrated circuits and electronic systems. Tharas Systems Hammer custom-processor based hardware-assisted verification solution works in conjunction with popular Verilog and VHDL-based software simulators from Synopsys (NASDAQ: SNPS), Cadence Design (NYSE: CDN) and Mentor Graphics (NASDAQ: MENT). Visit Tharas Systems at http://www.tharas.com. For more specific product information or call 1-408-855-3200.
Hammer(R) is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
|
Related News
- Siemens introduces Questa Verification IP solution support for the new CXL 3.0 protocol
- Truechip Introduces Automation Products - NoC Verification and NoC Performance - for Revolutionizing the Verification Spectrum
- Mentor introduces Calibre nmLVS-Recon technology to dramatically streamline overall IC circuit verification
- Tessolve strengthens its VLSI Design services with the acquisition of T&VS
- Avery Design Introduces CXL VIP
Breaking News
- Arm revenues up 47%; shares fall
- Sondrel awarded new Video Processor ASIC design and supply contract for a leading provider of High-Performance Video systems
- X-Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ - a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core
- Softbank reported to be in talks to buy Graphcore
- VESA Elevates PC and Laptop HDR Display Performance with Updated DisplayHDR Specification
Most Popular
- Synopsys Enters Definitive Agreement to Sell its Software Integrity Business to Clearlake Capital and Francisco Partners
- Fabless semiconductor startup Mindgrove launches India's first indigenously designed commercial high-performance MCU chip
- sureCore announces successful tape-out of cryogenic IP demonstrator
- Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
- Announcing Availability of Silicon-Proven 12bit 1Msps SAR ADC IP Core for Whitebox Licensing with Royalty Free
E-mail This Article | Printer-Friendly Page |