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New Silicon IP
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Ethernet TSN Switch IP Core - Efficient and Massively Customizable
- Full wire-speed on all ports for all Ethernet frame sizes.
- Store and Forward shared memory architecture.
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HBM3 PHY IP on TSMC N5
- Low latency, small area, low power
- Compatible with JEDEC standard HBM3 DRAMs
- Data rates up to 7200 Mbps
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eDP 1.5a RX PHY Samsung 14nm
- eDP v1.5a compliant
- Max. 8.1Gbps datarate supported
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DDR5 Registering Clock Driver (RCD) (DDR5RCD03)
- Compliance as per JEDEC's JESD82-513
- In I3C mode, SCL Operating speed 12.5MHz as Maximum
- DDR5 server speeds up to 6000MT/s
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16 bit, 5 Msps DAC
- 16-bit resolution
- Single ended, voltage output
- Rail to rail output buffer
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CAN XL Controller
- Designed in accordance with ISO 11898‐1:2024 specification (tbc) and CiA610-1 specification
- Supports CAN, CAN FD and CAN-XL frames
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Capless LDO regulator in TSMC 22ULL 1.8V
- Low silicon area
- Fast transient response
- Low-Power (LP) mode to supply AON domain
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High quality, low latency, secure video encoder for the transmission of HD video
- Supports all SMPTE non-interlaced standards from 720p/23 to 1080p/60.
- Supports YCbCr or RAW data formats.
- Can interface directly to image sensor.
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PCIe 6.0 PHY IP for TSMC N3E
- Supports the latest features of PCIe 6.0 specification
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- Certified according to ISO 26262:2018 edition series of standards
- RISC-V RV32GCBP Instructions
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20 mA LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V)
- TSMC EF CMOS 55nm
- High precision stabilization voltage
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On-chip memory expansion
- On-the-fly compression / decompression of cache lines
- Optional secureTraining on metadata capability
Top Silicon IP
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1
32-Bit RISC-V Embedded Processor and Subsystem. Maps ARM M-0 to M-4. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions
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High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
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3
RISC-V GPGPU for 3D graphics and AI at the edge
- Unparalleled RISC-V flexibility & programmability
- Compelling ultra-low power 3D for wearables & aiot
- Enabling your ai application without additional silicon cost
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High Image Quality Super Resolution IP
- Up to 8K @ 60 FPS
- Up to 4 pixels per clock
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32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- Ideal either as a Main Controller or a Safety Island in a Functional Safety System
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Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
- Drag & Drop Graphical User Interface
- Unified configuration tree view
- Intelligent routing path calculation
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MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
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On-chip memory expansion
- On-the-fly compression / decompression of cache lines
- Optional secureTraining on metadata capability
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General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- Certified according to ISO 26262:2018 edition series of standards
- RISC-V RV32GCBP Instructions
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ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- 32-bit RISC-V embedded CPU with a 5-stage pipeline
- DSP implementation to extend the RISC-V baseline (RMX-500D)
- 2 KB to 64 KB instruction & data L1 caches
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Securyzr™ Intrusion Detection System (IDS)
- Part of a global threat detection, analysis and response solution form Chip-to-Cloud relying on Securyzr™ iSSP (integrated Security Services Platform).
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