 |
PGC Adopts S2C's FPGA-based ESL Tools to Streamline Front-End Design Service Flow (Jul. 02, 2008)
Complementing proven strengths in back-end design, integrated chip (IC) fabrication, and production logistics, PGC will now employ S2C’s Virtex-5 TAI Logic Module to enact system-on-chip (SoC) design creation, verification, and customer sign-off capabilities on FPGA prototype. |
| |
CoWare Delivers Support for ARM Cortex-based Applications (Jun. 30, 2008)
Major Semiconductor and Mobile Phone Companies Rely on CoWare's ESL 2.0 Solutions for Optimizing ARM Cortex-based Designs |
| |
Virtutech Announces Breakthrough Hybrid Simulation Capability Allowing Mixed Levels of Model Abstraction (Jun. 16, 2008)
Supports Advanced Freescale QorIQ™ P4080 Multicore Processor; Hybrid Simulation Infrastructure Leverages Proven Simics® Simulator |
| |
Freescale Delivers Virtual Platforms to Continental Using CoWare ESL 2.0 Solutions (Jun. 03, 2008)
Standards-based Solutions for Pre-silicon Software Development Accelerate Collaborative Development of the Industry’s First Triple-Core Automotive MCU |
| |
Duolog Technologies Provides OCP-IP Members Powerful OCP Transaction Analysis Tool (May. 27, 2008)
Duolog Technologies and OCP-IP announce that Duolog will provide its OCP-Conductor Professional transaction analysis tool free of charge to members of OCP-IP. |
| |
Sonics Bundles JEDA OCP Checker Into SonicsStudio (May. 27, 2008)
The newly released SonicsStudio 4.8, Sonics’ SoC development tool, includes the JEDA OCPchecker, a SystemC based OCP compliance checker to pinpoints protocol violations under virtual platform simulation environments. |
| |
CoFluent Design Announces World's First Eclipse-Based Graphical ESL Modeling and Simulation Framework (May. 26, 2008)
CoFluent Studio Leverages Model-Driven Development and Eclipse Technologies to Deliver State-of-the-Art Graphical Modeling Environment and Superior Interoperability |
| |
EVE to Showcase Transaction-Level Modeling Capabilities During DAC (May. 20, 2008)
EVE is adding two new transactors to its extensive library of the most common standard protocols, an AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor. Both can be connected easily to the design, reducing the setup time for the testbench by eliminating the need for hardware speed bridges or synthesizable testbenches. |
| |
Synopsys Adds 30 New Titles to DesignWare System-Level Library (May. 15, 2008)
The new members of the Library include high-performance transaction-level models (TLMs) for PowerPC®, MIPS, and DesignWare IP. DesignWare System-Level Library models significantly reduce the time to create virtual platforms and are written in SystemC to work in any IEEE 1666 (SystemC)-compliant simulation environment. |
| |
CoWare and Agility Team to Accelerate the Simulation of Complex DSP Algorithms (May. 12, 2008)
CoWare is offering its customers integration support for accelerated C models generated by Agility’s RMS and MCS products into the entire range of CoWare’s ESL 2.0 solutions. |
| |
ChipVision Delivers Two Breakthrough ESL Power-Optimization Design Tools for Meeting Critical Power Budgets (Apr. 22, 2008)
The new tools are ideal for companies developing mobile communications, networking, consumer or automotive applications that need extended battery life or reduced cooling requirements. |
| |
CoWare Introduces First Ever Checkpoint / Restart Capability for Native SystemC Virtual Platforms (Apr. 14, 2008)
CoWare announced today the first ever checkpoint/restart capability for native SystemC Virtual Platforms. |
| |
NXP and CoWare Establish Strategic Relationship for the Company Wide Deployment of ESL Technologies (Apr. 07, 2008)
The strategic, multi-year relationship covers a broad spectrum of ESL technologies from CoWare as well as a major services agreement to support the rapid deployment of these technologies across NXP's business units. |
| |
CoWare and Sonics Release ESL 2.0 Upgrade of Joint Flow (Mar. 26, 2008)
Sonics SMART Interconnect Integration with CoWare ESL 2.0 Solution Provides Faster Time-to-Market for Production Designs |
| |
VaST and NEC Electronics America Develop Models of V850-Based Microcontrollers for Leading Automotive Customers (Mar. 17, 2008)
VaST Systems and NEC Electronics America today announced the availability and development of virtual models of NEC Electronics’ 32-bit V850™-based microcontroller units (MCUs). |
| |
Axilica Offers tool for behavioral synthesis of hardware designs from UML (Mar. 10, 2008)
FalconML is a powerful new tool developed by Axilica to deliver behavioural synthesis of FPGA or ASIC-directed hardware designs from UML. |
| |
CoWare Announces System-Level Design Solutions for Android-based Products (Feb. 27, 2008)
CoWare announced today its solution for the rapid design and development of chipsets, handsets and software applications built to support the Android™ Mobile Platform. |
| |
Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI) (Feb. 25, 2008)
Riviera-PRO offers mixed language verification support for VHDL, Verilog®, SystemVerilog and SystemC for behavioral, structural and timing simulation of multi-million gate ASIC and FPGA designs. |
| |
Carbon Becomes Fujitsu Cedar-ESL Services Partner (Feb. 20, 2008)
Carbon’s automatic model generation technology has been integrated into Fujitsu’s CedarTM-ESL Services. Carbon Model Studio creates SystemC models for electronic system level (ESL) environments, including those from ARM, CoWare, Synopsys, VaST and others, for Fujitsu’s application specific integrated circuit (ASIC) customers. |
| |
Synfora Moves Algorithmic Synthesis to the Next Level with PICO Extreme (Feb. 14, 2008)
PICO Extreme’s recursive system composition methodology is enabled by TCABs – tightly coupled accelerator blocks – that allow users to designate parts of their algorithm as custom building blocks. |
| |
EVE and CoWare Forge Strategic Alliance (Jan. 21, 2008)
EVE and CoWare today announced a strategic alliance to provide design teams with an integrated approach that ties hardware/software co-verification from EVE with SystemC virtual platforms developed with CoWare’s ESL 2.0 solutions. |
| |
CoWare and STARC Integrate SystemC TLM Methodology (Jan. 21, 2008)
CoWare announced the collaboration with STARC to support CoWare’s open SystemC modeling library APIs for the creation of reusable virtual platforms for architecture design and software development. |
| |
Esterel Studio, adopted at STMicroelectronics, enhances productive design for STBus and STNoC based control-intensive IP (Jan. 18, 2008)
Esterel EDA Technologies today announced that STMicroelectronics has applied Esterel Studio for the design of new components for the STBus and ST Network-on Chip (STNoC) within ST’s On-Chip Communication Systems (OCCS) team. |
| |
Synfora Integrates PICO Express with CoWare ESL 2.0 Solutions (Jan. 16, 2008)
Joint customers will use Synfora’s PICO Express to create synthesizable RTL and the corresponding transaction-level SystemC models from an untimed C algorithm for product-specific intellectual property (IP), and reuse them in combination with other ESL models in CoWare’s Platform Architect to capture the entire product platform at the system-level. |
| |
Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker (Jan. 14, 2008)
Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct |
| |
Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling (Dec. 04, 2007)
SystemC users urged to provide feedback on TLM-2 Draft 2 by January 31st |
| |
Synplicity Joins Xilinx ESL Design Ecosystem (Nov. 26, 2007)
The Synplify DSP environment facilitates high-level modeling and hardware abstraction, constraint-driven algorithm synthesis into RTL and powerful system-wide optimizations for performance, area, and multi-channelization tradeoff exploration. |
| |
CoWare and Tensilica Integrate Diamond Standard 106Micro with CoWare ESL 2.0 Technology (Nov. 20, 2007)
The integration provides designers with the first and most productive ESL 2.0 solution for platform architecture design, platform verification, and software development using Tensilica’s processor core with the smallest area, lowest power, and highest performance on the market. |
| |
Virtutech Accelerates and Streamlines Development of Applications for Next-Generation of IBM PowerPC Processor Cores (Nov. 14, 2007)
Virtutech today announced that its Simics™ product has been selected by IBM to create advanced, system-level simulation models for IBM’s next-generation embedded processor cores, beginning with the PowerPC 464FP core. |
| |
Carbon Design Systems Adds Support for Latest Version of ARM Tools (Nov. 12, 2007)
Its Carbon Model Studio generates hardware-accurate software models that integrate into RealView SoC Designer 7.0 release for rapid development and assembly of virtual platforms to explore architectural tradeoffs and perform pre-silicon software development. |
