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ESL handoff: closer than you think (Jul. 08, 2008)
Any viable design methodology requires tight links to implementation, and to meet this need a new generation of High-Level Synthesis tools is emerging, based on SystemC. |
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Leveraging OCP for Cache Coherent Traffic Within an Embedded Multi-core Cluster (Jul. 07, 2008)
Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. |
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Generic Driver Model using hardware abstraction and standard APIs (Jun. 30, 2008)
This paper describes a unique approach for developing drivers using hardware abstraction and standard APIs for hardware and software interfaces. |
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Leveraging Virtual Platforms for Embedded Software Validation: Part 2 (Jun. 26, 2008)
The article will discuss how to effectively use interface and abstraction techniques, modeling tools, debugging techniques, and profiling to characterize and validate architectures and embedded software. |
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Modelling Embedded Systems at Functional Untimed Application Level (Jun. 05, 2008)
We propose a structured methodology to allow flexible, accurate and fast system modelling at Functional Untimed Application Level. The methodology is built on 4 levels of abstraction, from the IP Level up to the Use-case Level, where the bottom level gives us accuracy, while the top gives us speed. |
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Adapter Based Distributed Simulation of Multiprocessor SoCs Using SystemC (Jun. 02, 2008)
An ever increasing demand for execution speed and communication bandwidth has made the multi-processor SoCs a common design trend in today’s computation and communication architectures. |
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ESL Methods for Optimizing a Multi-media Phone Chip (May. 27, 2008)
This article describes experiences with the adoption of ESL for optimizing the architecture of a multi-media cellular phone platform. |
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Debugging a Shared Memory Problem in a multi-core design with virtual hardware (May. 22, 2008)
With multicore systems becoming the norm, software developers have found the debugging of such systems, using a physical hardware development board, to be very challenging, particularly when it comes to the integration of applications sharing data across multiple cores. |
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Rapid Creation of Application Models from Bandwidth Aware Core Graphs (May. 19, 2008)
We present a methodology that allows the rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. |
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How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1 (May. 01, 2008)
Using advanced HDLs like SystemVerilog, current hardware modeling styles can be enhanced both in terms of abstraction levels and overall efficiency. |
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SystemC: Key modeling concepts besides TLM to boost your simulation performance (Mar. 24, 2008)
Virtualization of SoC, ECUs and other electronic systems is used to explore (micro-)architectures at system level as well as to develop and verify software early in the design cycle. |
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Electronic system-level approach shortens SoC design (Feb. 14, 2008)
The main reason for designing systems-on-chip at the electronic system level is to reduce time-to-market, development cost and power consumption. |
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Hardware design using ESL (Feb. 11, 2008)
To build increasingly sophisticated chips, engineers must be freed from low-level details and limiting methodologies. ESL design flows raise the level of abstraction from the register transfer level (RTL) to the system level. |
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Fast virtual platforms open up multicore software development (Feb. 11, 2008)
Virtual platforms aid the short-term market takeoff of multicore architectures as well as their long-term acceptance and success. |
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Accelerating High-Level SysML and SystemC SoC Designs (Feb. 04, 2008)
The goal of this research is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling techniques that should result in modeling both the structure and behavioral SysML diagram to produce a single executable that represents the system behavior. A prototype for a translation tool, a SysML model compiler, has been implemented using a UML editing tool that supports SysML. |
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Putting the system in electronic system design (Feb. 04, 2008)
Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation. |
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A Chip IP Integrator for System Level Design (Jan. 14, 2008)
This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. This paper shares the approach, methodology and the results on a real-life system comprising several RTL design blocks in Verilog each having around a quarter of million instances as well as on an ARM 4 CPU test chip design. |
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Viewpoint: RTL-ers should move to ESL (Oct. 22, 2007)
Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology experts within electronics companies whose sole responsibility was to move design teams to using RTL design methods. It was this focus that enabled the methodology shift the industry experienced and changed the way chips were designed. |
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How effective use of ESL tools can increase your HW/SW system design productivity (Oct. 05, 2007)
The use of Electronic System Level tools, complemented by techniques such as Sequential Logic Equivalence Checking (SLEC), will significantly improve system design productivity especially as designs move to geometries below 90 nanometers. |
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Design of a C library for the implementation of 3D graphics applications on a SoC (Sep. 17, 2007)
In this paper a new approach to the implementation of 3D graphics applications on a SoC architecture is described. This approach is meant to be particularly flexible, in order to be used in different kinds of systems: it is based on the realization of software libraries, that are developed using the C programming language. |
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Introduction to and Regression Test for OCP SystemC Channel Models (Sep. 04, 2007)
Using OCP, IP designers can make their cores independent of some specific bus protocols, and hence the IP cores will be suitable for any particular design implementation. This makes it easier to reuse OCP-compliant cores across multiple SOC designs. Traditionally designers have to support different bus protocols by modifying a core's interface, the verification suite, the test bench, the documentation, and all other interface-related design issues of the core. |
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Using an open debug interconnect model to simplify embedded systems design (Aug. 30, 2007)
An open debug interconnect model is proposed for understanding debugger component interactions. |
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Distributed Software Behaviour Analysis Through the MPSoC Design Flow (Aug. 27, 2007)
The complexity of developing Systems-on-Chip (Soc) is increasing continuously, but the productivity of hardware and software developers is not growing at a comparable pace. As a consequence, the conception of a new SoC can take a few years and software can’t wait its availability. |
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A New Methodology for Hardware Software Co-verification (Jul. 30, 2007)
Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers require these tools and software and it would be an expensive proposition for IP developers. |
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Transaction Level Model of the USB On-The-Go controller IP core (Jul. 23, 2007)
The paper describes a transaction level model of the serial bus controller compliant to USB On-The-Go specification [1]. The model has been developed as an abstraction of an existing IP core, written in VHDL. The possible use in the development or testing of a software driver was addressed too. |
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Commentary: SystemVerilog enables design with verification (Jun. 28, 2007)
The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. |
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Video codecs in SoCs using OCP-based programmable accelerator design (Apr. 30, 2007)
Flexibility is increasingly necessary when supporting multiple standards, such as the VC-1 and H.264 video codecs within a single SoC. This flexibility can be achieved by having programmable state machines instead of hardwired state machines. |
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Transaction Recording, Modeling and Extensions for SystemVerilog (Apr. 16, 2007)
This paper discusses ways to improve the adoption rate by improving the usability and simplifying the modeling concepts. Using SystemVerilog we demonstrate a simplified PLI interface for recording transactions and we extend previous language standard changes to improve automation. |
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A system-level verification flow for EDA (Mar. 19, 2007)
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions. |
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A Simple New Approach to Hardware Software Co-Verification (Mar. 05, 2007)
Coverage-driven verification (CDV) has generated remarkable interest in recent years. Because of its enormously comprehensive capabilities, more and more verification teams are now relying on the CDV approach. |
