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Latest EDA News

NextIO Standardizes on VMM Methodology and Synopsys VCS for Next-Generation I/O Virtualization Chip (May. 08, 2008) Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs. This complete verification environment enabled NextIO to achieve first-pass functional silicon success.

Cadence Delivers Silicon-Ready Reference Methodologies for ARM Cortex-A9 Processor (May. 02, 2008) Cadence Design Systems, Inc. today announced the immediate availability of multiple, silicon-ready RTL to GDSII implementation flows based on the Cadence® Encounter® digital IC design platform, for the ARM® Cortex™-A9 processor.

Synplicity Launches ReadyIP Program: The Industry's First Universal, Secure IP Flow for FPGA Implementation (Apr. 15, 2008) The ReadyIP program delivers the industry’s first and complete universal, encrypted design methodology for FPGA implementation, allowing users to incorporate and easily integrate IP from several third-party vendors within their designs using the Synplify Pro® and/or Synplify® Premier solutions, Synplicity’s industry-standard synthesis environments.

Synplicity Introduces System Designer: System-Level Implementation and IP Integration Tool for FPGA Design (Apr. 15, 2008) The System Designer™ capability allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices, including those from Actel, Altera, Lattice Semiconductor and Xilinx.

ClioSoft Introduces Enterprise Edition of the SOS Design Data Collaboration Platform (Apr. 11, 2008) SOS Enterprise Edition is aimed at addressing the needs of large distributed enterprises by providing integrated design data management for a variety of EDA tools, easing management of hierarchically distributed designs, facilitating reuse of intellectual property and ensuring immediate, live, virtual onsite support when needed.

NXP Semiconductors and IPextreme Launch Ground-breaking Methodology for Semiconductor IP Design (Apr. 02, 2008) IPextreme and NXP Semiconductors today announced the availability of NXP’s internally-developed CoReUse methodology and QCore™ tool for licensing to the entire semiconductor industry through IPextreme.

Synopsys Extends Design Compiler Topographical Technology to Predict and Alleviate Routing Congestion (Mar. 31, 2008) Design Compiler Graphical is the industry's first synthesis solution that predicts circuit congestion "hot spots" early in the design flow, provides designers with visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in these areas.

Mentor Graphics Expands Questa Functional Verification Platform with Questa Codelink for Processor-Driven Tests (Mar. 27, 2008) The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests.

Numetrics Unveils NMX-ERP 3.0, Next Generation ERP Software for Semiconductor IC Development Organizations (Mar. 24, 2008) New Software Measures Schedule Risk of 45nm IC Projects, Delivers Enhanced Staffing & Schedule Estimates, Introduces XML Interface for Enterprise-wide Integration

The MathWorks Expands Product Portfolio for Electronic System Verification (Mar. 24, 2008) EDA Simulator Link Products Now Provide System-Level Verification Workflow for Hardware Simulators from Synopsys, Mentor Graphics, and Cadence Design Systems

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