Fast, Efficient Hardware Debug for Programmable Logic Designs
In FPGA design today the final and often most difficult phase of FPGA system development is hardware debug in the laboratory. HDL simulators are used to uncover internal logic bugs, but cannot verify in-system device performance because of the difficulty of creating realistic vectors in the test bench.
In the past, designers have used logic analyzers to probe designs using device pins. More recently FPGA vendors have released debug tools that probe signals over the JTAG port. Each of these solutions requires you to manually edit your source code to add probes and to use a waveform viewer to check the results. The solutions are not well integrated with design synthesis or implementation tools and almost always require time consuming iterations.
What is needed is a suite of tools that work with logic synthesis in an environment where:
Nodes can be quickly located within a large design and appropriately tagged for monitoring.
Results are easily viewed and related back to the source code.
Design iterations swiftly implemented so that the debug team can fully concentrate on the design.
This white paper discusses the merits of current simulation and debug methodologies, as well as explores a new flexible and powerful approach that can ensure design integrity and robustness under actual system conditions.
Click here to access this paper (PDF file)
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