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SUNOpenSPARC T1 Version 1.2 Released!
 In version 1.2 the full source code for the SPARC Architectural Model (SAM) and Legion simulators is made available. SAM is a full system simulator useful for software bringup work on modified implementations. Legion is a fast instruction accurate simulator which provides a rapid means of developing and testing software functionality in absence of real hardware.

Download it now!

For the first time in history, developers gain access to the chip multi-threading (CMT) technology unique to the UltraSPARC T1 processor, which is released under the GNU General Public License (GPL). This new open source version of the UltraSPARC T1 design is called "OpenSPARC T1" and is a 64 bit, 32 threaded processor design available at no charge.
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  Free Protected IP Models

These models are protected models which can be run on simulation tools and platforms. It should allow you to get interest in these IPs and to explore if they fit in your design.

Core Name Core Description
DP8051 8-bit Pipelined RISC Microcontroller (speed optimized) from Digital Core Design
PLLXpert Online PLLXpert Online from ParthusCeva enables a designer to either create a custom PLL or alternatively download an existing PLL reference design that can be fine-tuned by the designer for a specific application.
Flip-SpRAM-LP-0.25 On-line Evaluation and Front-End view generation for a Single-Port RAM generator targeting TSMC - 0.25 um.
Dolphin Integration

  Open source, Free IP Cores Projects

  • OpenSPARC T1
      • OpenSPARC T1 is the open source version of the UltraSPARC T1 processor. The UltraSPARC T1 processor with CoolThreads technology is the highest-throughput and most eco-responsible processor ever created. It's a breakthrough discovery for reducing data center energy consumption, while dramatically increasing throughput. Its 32 simultaneous processing threads, drawing about as much power as a light bulb, give you the best performance per watt of any processor available.
       
  • LEON3 Processor - synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture
      • OPENCORES.ORG is a repository of open source, free IP synthesizable blocks and supplemental prototype boards. Most of our cores are currently under development but some are already available.
       
    ore
      Monitor and debug any internal signals within your FPGA design using a standard parallel-to-JTAG cable with this free IP core released under the GNU General Public License
       
  • GRLIB IP-Library - Configurable AMBA bus SoC platform
      • The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources. The full source code is available under the GNU GPL license, allowing free evaluation.
       
  • PXL-H264-ID31 - H.264 Inverse Integer Transform
      • The 2-D IIT core implements the algorithm by employing row-column decomposition of the data and applying a 1-D transform on the data row-wise, and then on the row results, column-wise.
       
  • Opencores.org
      • OPENCORES.ORG is a repository of open source, free IP synthesizable blocks and supplemental prototype boards. Most of our cores are currently under development but some are already available.