ESL Design And Verification 
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By Brian Bailey, Grant Martin and Andrew Piziali |
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Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set
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Luciano Lavagno (Cadence Berkeley Laboratories), Grant Martin (Tensilica Inc.) & Louis Scheffer (Cadence Design Systems)
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System Level Design Model with re-Use of System IP
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By Patrizia Cavalloro - Italtel SpA (Italy), Christophe Gendarme - Alcatel Bell (Belgium), Klaus Kronlöf - Nokia Research Center (Finland), Jean P. Mermet - ECSI (France), Jos van Sas - Alcatel Bell (Belgium), Kari Tiensyrjä - VTT Electronics (Finland), Nikolaos S. Voros - NTRACOM S.A. (Greece) |
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Winning the SoC Revolution
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By Grant Martin & Henry Chang - Cadence Design Systems (USA) |
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Systematic Design of Analog IP Blocks
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By Jan Vandenbussche - AnSem N.V. (Belgium), Georges Gielen - Katholieke Universiteit Leuven (Belgium) & Michiel Steyaert - Katholieke Universiteit Leuven (Belgium) |
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Intellectual Property Protection in VLSI Design - Theory and Practice
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By Gang Qu, University of Maryland, College Park, USA & Miodrag Potkonjak University of California, Los Angeles, USA |
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Design-For-Test For Digital IC's and Embedded Core Systems
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By Alfred Crouch |
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Modern VLSI Design: System-on-Chip Design
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By Wayne Wolf |
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Rapid Prototyping of Digital Systems
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By James O. Hamblen Georgia Institute of Technology, Atlanta, USA Michael D. Furman Georgia Institute of Technology, Atlanta, USA |
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System-on-a-chip Verification Methodology and Techniques
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By Prakash Rashinkar, Peter Paterson, Leena Singh Cadence Design Systems, Inc., San Jose, CA |
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Reuse Methodology Manual for Systems-On-A-Chip Designs
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By Pierre Bricaud, Michael Keating, Synopsys, Inc. |
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Surviving the SOC Revolution
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By Henry Chang, Larry Cooke, Merrill Hunt, Grant Martin, Andrew McNelly, Lee Todd |
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Reuse in Electronic Design : From Information Modelling to Intellectual Properties
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By Peter Conradi |
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Reuse Techniques for Vlsi Design
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By Ralf Seepold, Arno Kunzmann |
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