Friday Sep. 19, 2008
One on One: John Koeter
Next in our interview series, John Koeter offers insights on the IP market.
John Koeter joined Synopsys in 1998 and is currently Vice President of Marketing for the Solutions Group. In that capacity, he is responsible for the marketing of Synopsys' DesignWare® IP, Professional Services and System-Level Design products. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices. Mr. Koeter holds a BSEE degree from Cornell University.
John,
Thanks for sitting down with me and sharing your thoughts on the IP market. Synopsys is a unique success story in making IP work in the context of the large EDA company. Our readers are eager to hear your viewpoints of the market and where its going. Let's start.
1. As an IP company, what is your #1 challenge you have with your customers and what are you doing about it?
With IDMs moving to fab-lite or fabless, the natural inclination might be to think that there are fewer process options to support. In reality, we are seeing the opposite – the number of process options is growing rapidly as customers and foundries optimize their costs. In addition to the traditional full process nodes (130nm, 90nm, 65nm, 45nm, 32nm), half nodes are becoming commonplace. At 65nm and below, there are multiple metal stack options and different I/O voltages (2.5v, 1.8v) to support as well.
In addition to the expanding number of process options, the interface IP standards continue to evolve. Protocol transitions, such as DDR2 to DDR3; PCI Express 1.1 to 2.0 to 3.0; USB 2.0 to 3.0, etc. require multiple IP architectures per process option.
The good news for Synopsys is that this increasing number of process variants creates surging demand for our mixed signal products, making it the fastest growing part of our IP portfolio. The challenge is how to port the IP to many different process nodes rapidly and cost effectively.
To address this challenge, Synopsys has created a highly efficient analog porting “factory.” By starting with robust architectures that deliver good performance margins and yield combined with a CAD flow that is designed from the ground up to be highly efficient, Synopsys utilizes worldwide engineering talent to rapidly proliferate our IP. For example, in USB, we have ported our DesignWare USB nanoPHY to 16 different processes in the past 6 months.
Efficiently creating high quality IP in the required process and timeframe is one challenge but an equally important one is making the mixed signal IP easy to implement. To this end, Synopsys provides easy to integrate design views, detailed packaging/integration guidelines, production test vectors, I/O pads, and complete protocol solutions from the link layer to the PHY.
2. Putting the shoe on the other foot, what do you perceive as your customer’s # 1 challenge and what should they be doing about it?
Customers face many challenges in creating advanced SoCs. These include power optimization, schedule predictability, and the convergence of multiple functions on a single die, as well as complex verification and program management challenges. Addressing all of this while being under the cost pressures of a consumer-driven market and moving “upstream” to focus more resources on system architecture and software puts a tremendous amount of pressure on any design team.
High quality, third-party IP plays a key role in mitigating many of these challenges. By having a broad range of predefined, proven blocks, customers can focus resources on their core differentiation while lowering schedule risk and time-to-market. For these reasons, we increasingly see even the largest companies regularly outsourcing IP development.
3. The IP business model undergoes periodic attack from the media, do you think the IP business model is broken? Please elaborate.
The IP business model is not fundamentally broken, but it is evolving. As IP becomes an important part of their designs, we find that customers are looking to buy as much IP from a single, trusted vendor as possible. This enables the IP vendor to work together with its customers to create longer term, mutually beneficial business models that focus on collaboration, predictable revenue, and success sharing.
4. The IP market is dominated (revenue-wise) by a few large players, yet there remains hundreds of small outfits. Why is that?
The IP market is starting to mature. Part of that maturation is a consolidation of vendors who can provide larger solutions to customers and amortize development expenses over a larger customer base. Smaller companies offering specialized IP fulfill a role in this maturing market. There is often a need for design specific IP or unique IP that has a narrow market space. Smaller vendors can thrive profitably meeting these needs.
5. Should there be more or less IP companies?
I think that it is inevitable that there will be fewer IP companies over time. IP is growing increasingly complex, and the promised benefits of IP cannot be realized unless the IP provider has the necessary infrastructure and engineering expertise to develop very high quality IP and the ability to support it. Both of these facts point to additional vendor consolidation to be able to afford the investment levels required.
6. What role should EDA companies play in the IP market?
Synopsys views IP as an integral part of implementing complex SoCs. Tools, flows and IP are all mission critical to designer productivity and thus providing IP is a natural fit for the company.
7. What role should Service companies play in the IP market?
Services companies fulfill multiple roles in the IP market including integrating IP into a SoC (and verifying it in the system context), customizing IP for a particular system interface or other design need, and creating design-specific IP. As IP continues to get more complex, service companies will continue to play an important role in the growth of the IP market and the successful implementation of IP into chips. The chip aggregator, or ASIC-lite companies, also play a valuable role in the overall IP market by providing integration services and coordinating between the IP vendor, fab, packaging house and the customer to ensure successful implementation of the IC.
8. To what extent do you think the IP industry has come to grips with its quality issues?
I think that the answer to this question is vendor specific. In some areas of the IP market, the barriers to entry are low. In these situations, small IP companies or service firms may offer IP but often won’t have the time or resources to make the required investments to ensure high quality IP, often wrapping their IP with services to overcome the inevitable problems customers will have integrating it. It is quite costly to thoroughly verify a design in every mode, across every timing corner, with every configuration option and then validate it in silicon, take it through certification, interoperability testing and compliance testing. Scale becomes an important factor here. The larger IP providers like Synopsys can make the large investments required to enable high quality IP and support it.
9. Is there a need for greater standardization in IP?
There is already a significant amount of standardization in IP. Deliverables are released in de facto standard formats like Verilog, .lib, and GDSII. Guidelines for designing high quality, reusable IP are demonstrated in books like the Reuse Methodology Manual for System-on-a-Chip Designs. In interface IP, which is a focus for Synopsys, the IP has to conform to industry specifications from the USB-IF, PCI-SIG, and other standards bodies. We also work very closely with foundries to ensure compliance with their design rules and guidelines. We generally don’t see a need for greater standardization.
10. Ten years from now, what does the IP market look like?
Ten years is a long time in high technology. Here is our 3-5 year outlook:
• IP blocks will evolve into larger and larger blocks, ultimately becoming integrated subsystems or platforms. These larger IP components will inherently be more market specific
• Building larger subsystems will require more collaboration between IP companies to meet the needs of their customers
• Software content (from drivers to the application transaction layer) will significantly increase and will be provided by either the IP provider or a partner
• The ecosystem will mature with deeper collaboration between foundries and IP suppliers to enable faster time to market and manufacturable designs
• IP-based design methodology is common and EDA tools have adapted to very efficiently integrate and verify IP-based designs
• The use of higher levels of design abstraction (i.e., transaction-level models and virtual platforms) to model, analyze, and verify IP-based systems as well as develop embedded software pre-silicon is commonplace
• There are fewer IP companies, but those that remain are larger and stronger with viable business models
• There are close partnerships with customers to understand future IP/system needs. Large IP blocks/subsystems will be delivered with software and customization services.
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About the Author
Warren Savage, President and CEO of IPextreme, is a well-known and published authority in the field of semiconductor intellectual property.
He has a long history of pushing the envelope of design methodology from his work in fault tolerant computing at Tandem Computers in the 1980's and driving reliable design metholologies into commercial practice at Synopsys for its DesignWare IP product in the 1990s.
Much of his thinking became embodied in the seminal book on IP reuse, the Reuse Methodology Manual. Warren is taking his vision to the next level with his latest company, IPextreme, which is focused on enabling broad commercialization of IP captive in large semiconductor companies.
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