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On Cores
Meditations on the semiconductor and IP industries
By Warren Savage, CEO, IPextreme



Wednesday Aug. 22, 2007

Cindarella stood up at the System Verilog Ball

As I've written in this column before, a key impediment to System Verilog's application as a IP design language is uniform support across the major EDA players. Without a consistent set of implemented features and tested interoperability, IP design with System Verilog is too risky.

A significant step in System Verilog's maturity happened last week with the announcement that Cadence and Mentor have teamed to work together to develop the Open Verification Methodology around System Verilog. Bravo! With this move, the odds of System Verilog IP working across platform dramatically improve.

Oddly, Synopsys was not invited to the party and was left standing by the wall with a cup of fruit punch and no dance partner.

While a ménage à trios might be infinitely more interesting, perhaps this is the most practical way to make real progress for the industry. It’s difficult enough to have two large companies work together on something strategic for the entire industry, getting three competitors together on the same page is probably more than we can ask for. With solid progress by two, the third will inevitably follow. Let’s hope it’s the right two.



Posted by Warren Savage on Wednesday Aug. 22, 2007 | Add a Comment



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    • About the Author

    Warren Savage, President and CEO of IPextreme, is a well-known and published authority in the field of semiconductor intellectual property. He has a long history of pushing the envelope of design methodology from his work in fault tolerant computing at Tandem Computers in the 1980's and driving reliable design metholologies into commercial practice at Synopsys for its DesignWare IP product in the 1990s. Much of his thinking became embodied in the seminal book on IP reuse, the Reuse Methodology Manual. Warren is taking his vision to the next level with his latest company, IPextreme, which is focused on enabling broad commercialization of IP captive in large semiconductor companies.