Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore



Verification IP Articles

  • A comprehensive approach for verification of OCP-based SoCs (Feb. 08, 2005)
  • IP reuse requires a verification strategy (Feb. 08, 2005)
  • Addressing IP Reuse with Formal Verification and Assertion Based Verification (Jan. 21, 2005)
  • Is IP Quality Achievable, Measurable and Enforceable through the Design Chain? (Jan. 18, 2005)
  • True reuse moves well beyond recycling (VSIA) (Nov. 02, 2004)
  • Vendor Cooperation Necessary for Successful IP Implementation (Jul. 08, 2004)
  • Verification IP for IP verification (Jul. 08, 2004)
  • Platform-Based Design and Verification with Automated IP Integration (Jul. 08, 2004)
  • Best Practices for a Reusable Verification Environment (Jul. 08, 2004)
  • From The Outside In Making Third-Party IP Work in Semiconductor Design (Jul. 08, 2004)
  • Delivering verified AMBA AXI systems-on-chips (Jul. 08, 2004)
  • In-circuit SoC verification controls costs (Jul. 08, 2004)
  • Verifying SoCs and IP in parallel (Jul. 08, 2004)
  • Specs eye functional verification, quality (Jul. 08, 2004)
  • Verification = IP = Verification = IP =... - Part 2 (By Dr. Aart de Geus) (May. 14, 2004)
  • Testing 10GE in Transport Environments (Apr. 27, 2004)
  • Verification = IP = Verification = IP… - Part 1: Current Industry Situation and Drivers (Apr. 13, 2004)
  • The role of Verification IP in Complex core Design (Mar. 30, 2004)
  • Increased Verification Productivity through extensive Reuse (Mar. 12, 2004)
  • Panel ponders verification of IP (Mar. 03, 2004)
  • VSI Alliance Quality IP Metric (Feb. 16, 2004)
  • Functional Verification of a CAN data layer implementation: a case study (Feb. 10, 2004)
  • A Layered Verification Approach Applied to an AMBA-Based System (Dec. 09, 2003)
  • Attacking the Verification Challenge: Applying Next Generation Verification IP to PCI Express-based Design (by N. Mullinger, J. Hopkins & R. Hill from Synopsys) (Oct. 21, 2003)
  • Synopsys DesignWare Verification IP and Vera Accelerate Complex SoC Validation (Sep. 12, 2003)
  • Attacking the verification challenges: Applying next generation verification IP to bus protocol-based designs (Aug. 05, 2003)
  • Verifying PCI Express design IP (Jul. 21, 2003)
  • Automated verification of configurable IP blocks (Jul. 21, 2003)
  • Verification IP adapts to SoC complexity (Jul. 21, 2003)
  • Verification in the CoreWare suite (Jul. 21, 2003)


  • <A HREF="http://www.design-reuse.com/banner/exit.php?id=445" target="_top"><IMG SRC="http://www.us.design-reuse.com/adserver/www/images/eureka_static.jpg" WIDTH=125 HEIGHT=125 BORDER=0></A>