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H.264 encoder design using Application Engine Synthesis (May. 12, 2008)
The goal was to build an H.264 video encoder that would meet real-time requirements of 30 frames per second at D1 resolution with completion in less than 5 months. |
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An Efficient Software-Hardware Partitioning for Transport Demultiplexer (May. 05, 2008)
In this paper, we present an efficient software-hardware partitioning for transport demultiplexer. We develop transport demultiplexer software model and simulate it on reduced instruction set computer (RISC). |
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IP Core of On-line ICA Algorithm (May. 01, 2008)
We propose IP core of on-line ICA algorithm. The on-line ICA algorithm can decompose input signals into statistically independent components. We demonstrate that we can recover original chaotic signals from linearly mixed chaotic signals without any information of mixing. |
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System Packet Interface (SPI) 4.2 IP Core (Apr. 28, 2008)
The paper describes the architecture of a novel performance-enhanced SPI 4.2 IP Core. It also mentions, through examples and performance statistics, the improvement in the performance of SPI 4.2 data transfer as against the sub-optimal IP cores available. |
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Serial ATA and the evolution in data storage technology (Apr. 28, 2008)
No question, storage devices and storage technologies have helped fuel our digital lifestyle. The amount of storable information and the requirement for fast, efficient, state-of-the-art storage technologies are the primary mechanisms that must continue to evolve if we are to meet the demands for all things digital. |
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Overcome power, size and cost when developing optimized '4G' chipsets for handhelds (Apr. 24, 2008)
Here is an overview of three dimensions that should be addressed by 4G chip developers to minimize the power consumption, size and cost of their solutions. |
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FPGA-based flexible Ethernet switch reduces development time (Apr. 21, 2008)
The real time capability of networks that use the IEEE 1588 Precision Time Protocol is limited. This novel FPGA based switch eliminates the problem by implementing 1588 boundary/transparent clocks and gives developers the opportunity to leverage the flexibility of the FPGA to easily support multiple standards, quickly support standard changes and easily add custom features to the switch. |
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C-based coprocessor design, part 1: SIMD architecture (Apr. 17, 2008)
Here's how CebaTech's C2R C-to-RTL compiler was used to implement a G723.1 and G729.A speech coding accelerator. The accelerator, which attaches to a scalar processor core, features configurable micro-architecture and instruction-set architecture. |
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DDR3 memory - How to Win with Low Power and Reduced Thermal Solutions (Apr. 14, 2008)
The power struggle between DDR2 and DDR3 continues the tradeoff game between bandwidth and latency. The timing shifts required by the DDR3 flyby topology change the time at which byte lanes demand power by utilizing additional Delay Lock Loop within the controller itself. |
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Interfacing High Performance 32-bit Cores To MCU-based Memory Architectures (Apr. 11, 2008)
In transitioning from 8 to 32-bit MCU cores, a problem area is how to also improving FLASH memory to match. Here are some efficient methodologies the architect can employ to unclog the performance bottleneck. |
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High Level Synthesis of JPEG Application Engine (Apr. 02, 2008)
High Level Synthesis (HLS) technology and tools are used to transform high level behavioral model written in C, to synthesizable hardware in RTL . We have evaluated one such commercial HLS tool to create JPEG encoder RTL straight from C algorithm within a very short design time. This paper discusses the steps involved in automatic “Algorithm to RTL” transformation and compares the results with RTL developed using traditional method. |
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Reconfigurable radios, part 1: SDR architectures (Mar. 31, 2008)
The article makes the case for software defined radio (SDR), and discusses strategies for balancing flexibility, energy efficiency and spectrum use. It looks at different hardware architectures, including a multicore solution, as well as reconfigurable analog front ends. |
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Chip design lacks system predictability (Mar. 24, 2008)
We are at a crossroads in the semiconductor industry, where the difficulty in meeting chip design deadlines is not a lack of proper skills or mature EDA tools, but rather a more insidious demon. |
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Software-Defined Radio Platforms (Mar. 24, 2008)
The IMEC research center has demonstrated a large-scale design of a Software-Defined Radio (SDR). |
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A 0.79-mm2 29-mW Real-Time Face Detection IP Core (Mar. 20, 2008)
A 0.79-mm2 29-mW real-time face detection IP core is fabricated in a 0.13-mm CMOS technology and its performance was evaluated. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. |
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Multimedia display development for automotive and industrial apps speeded by FPGA-plus-IP platform (Mar. 17, 2008)
A flexible development platform for auto infotainment and other apps includes modules to send video to rear seat displays, transmit infrared sound, view a remote camera or develop touch screen control systems. |
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A Configurable HW/SW Platform for Video Application (Mar. 06, 2008)
This paper presents a dedicated hardware platform for a fast video and image data processing to real time application. The platform supports simultaneous HW/SW codesign and partitioning and based on the FPGA technologies and on a RISC processor. This reduces application design cycle. As an example, the H.263 video encoder is presented |
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The good? The bad? The ugly? IP Perspectives from Vendor to SOC Designer (Mar. 03, 2008)
While the IP landscape will always look different when seen through the eyes of SOC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This article explores the perspectives of three such players and their different ways of working with IP with an eye to making life with IP easier for everyone. |
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Dual Mode SMIA/MIPI Receiver Supporting 2Gbps (Feb. 28, 2008)
A two data-lane Serial Video Receiver (SVR), compatible with both MIPI CSI2 and SMIA CCP2 standards, with speeds of up to 2Gbps, is presented. |
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Improving design turn around time on a complex SoC by leveraging a reusable low power specification (Feb. 25, 2008)
This paper presents an approach to power design specification intent and associated enabled design methodologies that allow a scalable implementation of voltage islands. |
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Enhanced Capacitor Cross Coupled Front-End (Feb. 21, 2008)
This paper presents two approaches to improve the performance of RF low noise amplifiers (LNAs) and downconversion mixers. One approach is for noise enhancement and the other is for improving flatness of very wide range LNA |
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Secure Your Security Key in On-Chip SRAM: Techniques to avoid Data Remanance Attacks (Feb. 18, 2008)
Security protection in modern microcontroller’s logic devices with memories is based on the assumption that information from the memory disappears completely after erasing or when the power to the memory is removed. |
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Designing digital video broadcast and wireless systems with common FPGA building blocks (Feb. 14, 2008)
A digital communication system shares many similar building blocks that comprise a digital TV transmission system design. These key building blocks begin with channel coding and modulation techniques. It is these similarities that make it easier to take existing design blocks from one system and modify them for use in another one. |
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IPGenius, an on-line IP generation platform (Feb. 14, 2008)
We present an on-line tool for the generation of Configurable IP modules that can be used in Semiconductor devices. This tool allows the generation of customized IP modules, configured according to user requirements which are packaged and delivered to the end-user via the Internet. |
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Building High-Quality, Mixed-Signal IP in 65-nm and Beyond (Feb. 11, 2008)
This paper presents some key concepts necessary to design and build high-quality mixed-signal IP in 65‑nm or smaller geometries. The paper addresses design, layout, and verification techniques—with a focus on low-power design, reliability, and yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property (MSIP) portfolio. |
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Software - The X factor (Feb. 07, 2008)
This paper discusses the challenges faced by IP providers and/or SoC designers in providing appropriate software enabling customers to program their chips in the applications. Provision of such software is a critical success factor for many semiconductor businesses and this paper raises some of the issues together with some best practice example solutions. |
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Understanding the LIN PHY (physical) layer (Feb. 07, 2008)
The physical layer of the Local Interconnection Network is a key part of this automotive networking standard; it has unique attributes of which designers should be aware. |
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UWB Time-interleaved ADC exploiting SAR (Jan. 31, 2008)
The current technology trend for Analog-to- Digital Converters (ADCs) is particularly keen on power reduction, together with high-speed performance. The goal of the paper is to demonstrate that both the features can be achieved by a time-interleaved ADC architecture exploiting Successive Approximation (SA) algorithm. |
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Mixed Signal Drivers for Ultra Low Power and Very High Power Applications (Jan. 28, 2008)
Evolving niche markets, such as ICs for biomedical applications, are very challenging in respect to power consumption and on chip power dissipation, namely, wide range from ultra low power (ULP) functionality (<uW) where IC is battery powered, e.g. mobile micro transducers, to very high power (VHP, >5W), e.g. coded energy transfer from RFID¡¯s for remote sensing and animal tracking. |
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Analog IP: The changing technology scene (Jan. 28, 2008)
Those who have been observing last year’s activity in the analog IP space would readily infer the growing relevance and importance of Analog IP to the semiconductor development eco-system. Interestingly, the digital world needs more analog, and a healthy Analog IP eco-system is a critical enabler to innovation at the system-on-chip level. |
