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20 Most Popular Articles

Updated: Tue, 14 Oct 2008 01:00:02 +0200

Today		Yesterday
	1	4	DesignTag: A Thermally Sensed Security Tag to Protect Chip Designs This paper introduces a novel "security tag" technology for detecting misuse of semiconductor intellectual property, in the form of a small circuit which is added to the chip design.
	2	1	How to calculate CPU utilization How to calculate CPU utilization
	3	New!!!	EDA needs functional qualification EDA needs functional qualification, a new category of EDA product. The technology is fundamentally different from existing coverage technologies. The implications for the verification profession could be radical.
	4	11	Replacing obsolete video game circuits with Xilinx CPLDs In this article, the author replaces a defective part in a 1980s game system to show his employer that they can replace a range of parts that vendors are no longer producing.
	5	3	FPGA design from scratch I have been designing ASICs for more than 15 years. A few years ago I started to realize that there is another player in town and that is the FPGA circuit. With increasing NRE costs and with the long turn-around times, ASIC designs have become high-risk projects. At the same time FPGAs are getting bigger and faster and many companies have therefore decided to only use FPGAs.
	6	New!!!	What's your sine? Finding the right algorithm for digital frequency synthesis on a DSP A new approach to direct digital frequency synthesis uses a combination of lookup tables and trigonometric identities that lends itself to more efficient implementation on digital signal processors.
	7	New!!!	Silicon for better DTV tuning, PIP, speed and size Silicon tuners now have the edge, and offer feature advantages like inexpensive PIP via time slicing.
	8	5	FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand
	9	New!!!	A comparison of Network-on-Chip and Busses This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures
	10	New!!!	Microcontroller Applications -> Microcontrollers craft a networked future Microcontroller Applications -> Microcontrollers craft a networked future
	11	New!!!	Tutorial on Designing Delta-Sigma Modulators: Part 1 Tutorial on Designing Delta-Sigma Modulators: Part 1
	12	7	Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 This paper will review the new DDR3 features and compare and contrast them to previous features available in the DDR2 specification. One of the biggest changes is the in Physical Layer (PHY) portion of the memory interface and these changes will be high-lighted and illustrated with an example design of a high performance processor interface. The areas where backwards compatibility should be maintained will also be illustrated with an example design, showing how simple changes can provide significant benefits in re-use and system flexibility.
	13	New!!!	A Platform Based SoC Design Environment We present a reusable integrated design environment for platform-based SOC designs. This paper addresses issues faced and benefits of reusable and SOC design environment for getting a verification closure, synthesis and timing analysis in a platform-based SOC.
	14	2
	15	New!!!	Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN
	16	8	FPGA programming step by step FPGA programming step by step
	17	New!!!	An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs In this paper, we present a work in progress to provide high level modeling of PDR and a design flow to automatically generate VHDL code from these high level models depending on QoS criteria such as reconfiguration time, performance and power consumption.
	18	20	FPGA Clock Schemes FPGA Clock Schemes
	19	New!!!	Encrypting data with the Blowfish algorithm Encrypting data with the Blowfish algorithm
	20	16	Systolic FIR Filter Based FPGA In this paper, we review in detail the basic building blocks of reconfigurable devices, essentially, the field-programmable gate arrays, then we describes a high-speed, reconfigurable Systolic Finite Impulse Response Filter design implemented in the Virtex-II series of FPGAs.