 |
How to implement double-precision floating-point on FPGAs (Oct. 04, 2007)
The real results of a double-precision matrix multiply core that can easily be extended to a full DGEMM benchmark are demonstrated. |
| |
How to turn every FPGA LVDS pair into a complete SERDES solution (Sep. 27, 2007)
An innovative new technology called Align Lock Loops (ALLs) forms the basis for implementing fast, simple, and affordable chip-to-chip and board-to-board communication. |
| |
How to use FPGAs for quadrature encoder-based motor control applications (Sep. 13, 2007)
The accuracy and performance of quadrature encoders are superior to traditional solutions in high-speed motor control schemes. |
| |
Top-down DSP design for FPGAs (Sep. 06, 2007)
High-level C++ synthesis in combination with FPGAs is an attractive solution for achieving a rapid path from C++ to RTL running in hardware |
| |
Polyphase Video Scaling in FPGAs (Sep. 06, 2007)
This article gives a basic overview of polyphase video scaling followed by a detailed description of how to implement polyphase scaling in an FPGA. |
| |
FPGA design from scratch (Sep. 03, 2007)
I have been designing ASICs for more than 15 years. A few years ago I started to realize that there is another player in town and that is the FPGA circuit. With increasing NRE costs and with the long turn-around times, ASIC designs have become high-risk projects. At the same time FPGAs are getting bigger and faster and many companies have therefore decided to only use FPGAs. |
| |
How to support multiple SD devices using CPLDs (Aug. 23, 2007)
This tutorial details a scalable, auto-sensing bidirectional multiplexer-based CPLD-based design that allows host devices to support any number of SD devices. |
| |
Implementing an FPGA-based scalable OFDMA engine for WiMAX (Aug. 23, 2007)
The underlying nature of OFDMA is ideal for an FPGA-based WiMAX basestation design PHY. By leveraging a scalable OFDMA engine, engineering teams can save up to 18 months of development time. FPGA building blocks include bit-level, OFDMA symbol-level and digital intermediate frequency processing blocks. |
| |
Accelerate system performance with hybrid multiprocessing and FPGAs (Aug. 13, 2007)
Multiprocessing is becoming a key differentiator for FPGA-based processor architectures. |
| |
Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge (Jul. 11, 2007)
As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays. |
| |
An FPGA design flow for video imaging applications (Jul. 05, 2007)
This tutorial examines some of the challenges when implementing video applications in FPGAs and details how certain tools can be used to alleviate key design challenges. |
| |
Mixed-signal FPGAs provide GREEN POWER (Jul. 02, 2007)
Electric motors are used in nearly everything, from elevators to home appliances, but many are inefficient and waste a substantial amount of the power they consume. |
| |
Using FPGAs to interface with digital communication protocols (Jun. 07, 2007)
Custom digital protocols are commonly used for device or sub-system communications; this tutorial describes the FPGA-based implementation of such a protocol |
| |
Floating- to fixed-point MATLAB algorithm conversion for FPGAs (Jun. 04, 2007)
Here's how to accelerate fixed-point model generation and verification using the AccelDSP Synthesis tool. |
| |
A tutorial on tools, techniques, and methodology to improve FPGA designer productivity (Apr. 26, 2007)
Providing the ability to quickly understand the timing state of a design is crucial to the effectiveness of any FPGA design environment. |
| |
Programmable Logic: FPGAs get flexible for PCI Express (Apr. 18, 2007)
As the electronics industry shifts from the widely used PCI standard to PCI Express, FPGA vendors are poised to capitalize on the rapid expansion. They are offering products that address a range of system costs needs in various sectors, including PC, networking, industrial automation, medical and graphics/image processing. |
| |
How to test the interconnections between FPGAs on a high-density FPGA-based board (Apr. 12, 2007)
On a high-density FPGA-based board where multiple FPGAs are interconnected with hundreds of signals, checking and validating the interconnections between the FPGAs becomes a very challenging task. This article describes how challenging the problem is and also suggests a simple, effective, and generic solution to check the signal connectivity between the FPGAs. |
| |
Improving ASIC Design Verification using FPGAs and Structured ASICs (Apr. 10, 2007)
Prototyping an ASIC or SoC design using field programmable gate arrays (FPGAs) can relieve the time bottleneck and remove the high caliber compute resources required to verify the functionality of medium-to-large sized designs. A single FPGA prototype, for example, can serve to verify hardware, firmware, and application software design functionality before first silicon is received in-house. |
| |
Expanding applications for low-cost FPGAs (Apr. 05, 2007)
The need for, and approaches to, providing enhanced low-cost FPGA capability in the areas of SERDES, DSP, high-speed source synchronous I/O, memory capacity, and device configuration |
| |
Utilizing FPGAs in an IEEE 1588 precision time control implementation (Apr. 02, 2007)
The IEEE 1588 Standard Precision Time Protocol (PTP) is being used by industrial automation applications for precise time synchronization (PTS) on Ethernet networks. PTS provides accurate time synchronization for distributed control nodes. A triple-speed Ethernet medium access control (MAC) is essential for supporting the IEEE 1588 Standard. |
| |
High Density FPGA Package BIST Technique (Mar. 29, 2007)
Over 81% of new digital designs utilize Field Programmable Gate Arrays (FPGAs). With FPGA packages exceeding 1,000 pins, with Ball Grid Array (BGA) solder bumps providing the interconnect, it is vitally important to make solid contact with the Printed Circuit Board (PCB). |
| |
How programmable logic is finding its way into handsets (Mar. 22, 2007)
Already in mobile communication applications such as software defined radio (SDR), it is only a matter of time before FPGAs will appear in the broad base handset market. |
| |
Triple play - How FPGAs can tackle the challenges of network security (Mar. 15, 2007)
New classes of problems, such as network security, with an ever-changing complexion will arise, demanding novel, high performance, and cost-sensitive solutions. |
| |
How to map the H.264/AVC video standard onto an FPGA fabric (Mar. 05, 2007)
Despite its promise of improved coding efficiency over existing standards, H.264/AVC still presents engineering challenges. |
| |
How to improve design-level security with low-cost non-volatile FPGAs (Mar. 01, 2007)
Design-level security features in 90nm non-volatile Spartan-3AN FPGAs from Xilinx address the issues of overbuilding, cloning, and reverse engineering. |
| |
Getting the most out of ASIC prototyping with FPGAs (Feb. 08, 2007)
This tutorial discusses various issues that must be taken into account when using an FPGA to prototype an ASIC or SoC design. |
| |
Designing with Virtex-5 Embedded Tri-Mode Ethernet MACs (Feb. 05, 2007)
In this article, we’ll review the feature set of Ethernet MAC blocks in Virtex-5 devices. We’ll also describe the differences between Virtex-5 and Virtex-4 FX Ethernet MACs, illustrate some potential applications, and describe how to use standard Xilinx tools to integrate an Ethernet MAC into your design. |
| |
Designing custom embedded multicore processors (Feb. 01, 2007)
There are ''multi'' paths a designer can take to get the needed performance. |
| |
Design Security in Stratix III Devices (Jan. 25, 2007)
To make the Stratix III design security solution more secure and to protect the AES key, many security features have been implemented. The solution has been reviewed by external security consultants during the design phase and improvements have been made based on their feedback. This white paper details the security protection provided by the Stratix III design security solution. |
| |
How to design 65nm FPGA DDR2 memory interfaces for signal integrity (Jan. 25, 2007)
Practical techniques for ''correctness by design'' in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success |
