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Fast Virtual Prototyping for early software design and verification (Feb. 26, 2007)
This paper describes a simplified and novel approach for fast and easy virtual prototyping which provides a fully functional and accurate platform for the embedded software developer. This platform enables the software developer to execute the same binary image on the virtual platform as he would on the real hardware. The virtual platform, thus developed, can also be used for meaningful development of newer software features and upgrades, and will carry a lot of value for software development. |
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System simulation speeds application development (Feb. 26, 2007)
The wide range of different types and models of mobile phones can be a significant problem for developers of software. While the majority of phones are based on the ARM processor architecture, there are many different implementations with processor cores from the ARM9 and ARM11 families, and different ranges of peripherals from suppliers such as Texas Instruments, Qualcomm or Atmel. |
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Accelerated IP Model Development (Feb. 22, 2007)
IP-based SOC designs are increasingly dependent upon ESL methodologies to balance the constantly increasing pressure on both schedule and design complexity. In order to meet these demands, system models need to be generated rapidly and delivered to the teams developing the architecture, coding the implementation and validating the software. This paper will discuss a method for accelerating the development and validation of these complex system models. |
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Plan your verification with SystemVerilog (Feb. 19, 2007)
As verification engineers move to more-sophisticated techniques for system-on-chip (SoC) designs, their planning process is evolving as well. Traditional test-based planning is being supplanted by more sophisticated verification plans tracking coverage and assertions. One factor in this change is the widespread adoption of SystemVerilog, which supports the specification of functional coverage points, assertions and testbench constraints. |
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Programmable accelerators: hardware performance with software flexibility (Feb. 01, 2007)
Programmable accelerators combine the performance of custom hardware with the flexibility of software--and they are surprisingly easy to design. This article shows how to specify, profile, and debug a programmable accelerator, all in a matter of weeks. |
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Defining the TLM-to-RTL Design Flow (Jan. 18, 2007)
As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron implementation technology have semiconductor and system companies searching for new electronic system level (ESL)-based design flows. |
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How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time (Dec. 07, 2006)
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker. |
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''Enterprise'' System Level (ESL) Verification -- PART II (Dec. 04, 2006)
Hardware and embedded software development at the system-level will only require more verification cycles and proven methodologies to adhere to the specification to expose system-level errors and manage overall project risk |
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We Need ''Enterprise'' System-Level Solutions (Nov. 23, 2006)
To close the gaps in systems development across distributed design and verification teams it will become necessary to plan, design, and verify embedded software closer in-line with the way we currently design and verify hardware. |
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Fit the hardware to the algorithm with SystemC models (Oct. 12, 2006)
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Getting Practical with ESL Design Methodologies (Sep. 21, 2006)
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SystemVerilog Reference Verification Methodology: VMM Adoption (Sep. 04, 2006)
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Complex DSP system modeling made easy (Aug. 31, 2006)
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How to use UML in your SoC hardware/software design: Part 1 (Jul. 17, 2006)
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Legacy RTL brought into system-level flow (Jun. 27, 2006)
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Cycle Accuracy Analysis and Performance Measurements of a SystemC model (Jun. 19, 2006)
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A Case Study in Rule-Based Modeling (Jun. 15, 2006)
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SystemVerilog reference verification methodology: ESL (Jun. 12, 2006)
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Efficient creation of peripheral simulation from specifications (Jun. 05, 2006)
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Automated video algorithm implementation (Jun. 02, 2006)
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A bridging model for ESL synthesis (May. 30, 2006)
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A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs (May. 22, 2006)
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Sequential equivalence checking supports ESL flow (May. 15, 2006)
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SystemVerilog reference verification methodology: RTL (May. 01, 2006)
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Implementation of a SystemC Assertion Library (Apr. 10, 2006)
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SystemVerilog reference verification methodology: Introduction (Mar. 27, 2006)
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Managing Complexity with SystemC (Mar. 09, 2006)
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The 'what' and 'why' of transaction level modeling (Feb. 27, 2006)
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ESL Requirements for Configurable Processor-based Embedded System Design (Jan. 30, 2006)
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Integrating a Multi-Vendor ESL-to-Silicon Design Flow Using SPIRIT (Jan. 16, 2006)
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