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How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1 (May. 01, 2008)
Using advanced HDLs like SystemVerilog, current hardware modeling styles can be enhanced both in terms of abstraction levels and overall efficiency. |
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SystemC: Key modeling concepts besides TLM to boost your simulation performance (Mar. 24, 2008)
Virtualization of SoC, ECUs and other electronic systems is used to explore (micro-)architectures at system level as well as to develop and verify software early in the design cycle. |
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Electronic system-level approach shortens SoC design (Feb. 14, 2008)
The main reason for designing systems-on-chip at the electronic system level is to reduce time-to-market, development cost and power consumption. |
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Hardware design using ESL (Feb. 11, 2008)
To build increasingly sophisticated chips, engineers must be freed from low-level details and limiting methodologies. ESL design flows raise the level of abstraction from the register transfer level (RTL) to the system level. |
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Fast virtual platforms open up multicore software development (Feb. 11, 2008)
Virtual platforms aid the short-term market takeoff of multicore architectures as well as their long-term acceptance and success. |
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Accelerating High-Level SysML and SystemC SoC Designs (Feb. 04, 2008)
The goal of this research is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling techniques that should result in modeling both the structure and behavioral SysML diagram to produce a single executable that represents the system behavior. A prototype for a translation tool, a SysML model compiler, has been implemented using a UML editing tool that supports SysML. |
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Putting the system in electronic system design (Feb. 04, 2008)
Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation. |
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A Chip IP Integrator for System Level Design (Jan. 14, 2008)
This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. This paper shares the approach, methodology and the results on a real-life system comprising several RTL design blocks in Verilog each having around a quarter of million instances as well as on an ARM 4 CPU test chip design. |
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Viewpoint: RTL-ers should move to ESL (Oct. 22, 2007)
Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology experts within electronics companies whose sole responsibility was to move design teams to using RTL design methods. It was this focus that enabled the methodology shift the industry experienced and changed the way chips were designed. |
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How effective use of ESL tools can increase your HW/SW system design productivity (Oct. 05, 2007)
The use of Electronic System Level tools, complemented by techniques such as Sequential Logic Equivalence Checking (SLEC), will significantly improve system design productivity especially as designs move to geometries below 90 nanometers. |
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Design of a C library for the implementation of 3D graphics applications on a SoC (Sep. 17, 2007)
In this paper a new approach to the implementation of 3D graphics applications on a SoC architecture is described. This approach is meant to be particularly flexible, in order to be used in different kinds of systems: it is based on the realization of software libraries, that are developed using the C programming language. |
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Introduction to and Regression Test for OCP SystemC Channel Models (Sep. 04, 2007)
Using OCP, IP designers can make their cores independent of some specific bus protocols, and hence the IP cores will be suitable for any particular design implementation. This makes it easier to reuse OCP-compliant cores across multiple SOC designs. Traditionally designers have to support different bus protocols by modifying a core's interface, the verification suite, the test bench, the documentation, and all other interface-related design issues of the core. |
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Using an open debug interconnect model to simplify embedded systems design (Aug. 30, 2007)
An open debug interconnect model is proposed for understanding debugger component interactions. |
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Distributed Software Behaviour Analysis Through the MPSoC Design Flow (Aug. 27, 2007)
The complexity of developing Systems-on-Chip (Soc) is increasing continuously, but the productivity of hardware and software developers is not growing at a comparable pace. As a consequence, the conception of a new SoC can take a few years and software can’t wait its availability. |
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A New Methodology for Hardware Software Co-verification (Jul. 30, 2007)
Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers require these tools and software and it would be an expensive proposition for IP developers. |
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Transaction Level Model of the USB On-The-Go controller IP core (Jul. 23, 2007)
The paper describes a transaction level model of the serial bus controller compliant to USB On-The-Go specification [1]. The model has been developed as an abstraction of an existing IP core, written in VHDL. The possible use in the development or testing of a software driver was addressed too. |
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Commentary: SystemVerilog enables design with verification (Jun. 28, 2007)
The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. |
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Video codecs in SoCs using OCP-based programmable accelerator design (Apr. 30, 2007)
Flexibility is increasingly necessary when supporting multiple standards, such as the VC-1 and H.264 video codecs within a single SoC. This flexibility can be achieved by having programmable state machines instead of hardwired state machines. |
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Transaction Recording, Modeling and Extensions for SystemVerilog (Apr. 16, 2007)
This paper discusses ways to improve the adoption rate by improving the usability and simplifying the modeling concepts. Using SystemVerilog we demonstrate a simplified PLI interface for recording transactions and we extend previous language standard changes to improve automation. |
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A system-level verification flow for EDA (Mar. 19, 2007)
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions. |
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A Simple New Approach to Hardware Software Co-Verification (Mar. 05, 2007)
Coverage-driven verification (CDV) has generated remarkable interest in recent years. Because of its enormously comprehensive capabilities, more and more verification teams are now relying on the CDV approach. |
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Demystifying ESL for embedded systems designs (Mar. 01, 2007)
While the definitions of ESL may vary, the end result should be the same, namely letting system developers analyze their designs at a higher level of abstraction. |
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Use ESL synthesis techniques to replace dedicated DSPs with FPGAs (Mar. 01, 2007)
If your application isn't the most compute intensive, you may find that using an FPGA as a replacement is a good idea.
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Fast Virtual Prototyping for early software design and verification (Feb. 26, 2007)
This paper describes a simplified and novel approach for fast and easy virtual prototyping which provides a fully functional and accurate platform for the embedded software developer. This platform enables the software developer to execute the same binary image on the virtual platform as he would on the real hardware. The virtual platform, thus developed, can also be used for meaningful development of newer software features and upgrades, and will carry a lot of value for software development. |
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System simulation speeds application development (Feb. 26, 2007)
The wide range of different types and models of mobile phones can be a significant problem for developers of software. While the majority of phones are based on the ARM processor architecture, there are many different implementations with processor cores from the ARM9 and ARM11 families, and different ranges of peripherals from suppliers such as Texas Instruments, Qualcomm or Atmel. |
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Accelerated IP Model Development (Feb. 22, 2007)
IP-based SOC designs are increasingly dependent upon ESL methodologies to balance the constantly increasing pressure on both schedule and design complexity. In order to meet these demands, system models need to be generated rapidly and delivered to the teams developing the architecture, coding the implementation and validating the software. This paper will discuss a method for accelerating the development and validation of these complex system models. |
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Plan your verification with SystemVerilog (Feb. 19, 2007)
As verification engineers move to more-sophisticated techniques for system-on-chip (SoC) designs, their planning process is evolving as well. Traditional test-based planning is being supplanted by more sophisticated verification plans tracking coverage and assertions. One factor in this change is the widespread adoption of SystemVerilog, which supports the specification of functional coverage points, assertions and testbench constraints. |
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Programmable accelerators: hardware performance with software flexibility (Feb. 01, 2007)
Programmable accelerators combine the performance of custom hardware with the flexibility of software--and they are surprisingly easy to design. This article shows how to specify, profile, and debug a programmable accelerator, all in a matter of weeks. |
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Defining the TLM-to-RTL Design Flow (Jan. 18, 2007)
As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron implementation technology have semiconductor and system companies searching for new electronic system level (ESL)-based design flows. |
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How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time (Dec. 07, 2006)
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker. |
