Vendor Cooperation Necessary for Successful IP Implementation

The technical requirements for successfully implementing a complex standards-based silicon intellectual-property (IP) core in an electronic design automation tool flow are difficult. Along with verifying that the isolated core complies with required industry operating specifications, the IP vendor also must make sure that, when implemented in an EDA tool flow, the core still achieves its advertised performance. The business challenges for IP implementation are equally complex and can be harder to overcome.

In today's IP market, collaboration between IP and EDA vendors is necessary for maximizing product quality. If these vendors have multiple business agendas, however, this is not straightforward. For example, an EDA vendor might also offer IP products. This can put the vendor in the awkward position of being a partner and a competitor of the IP customer. In attempting to verify IP in such a tool vendor's flow, collaboration on solving IP integration issues might not be as forthcoming or the IP might be contaminated. These potential problems can lengthen the time it takes the IP vendor to verify compliance with the standard and lower the IP customer's confidence.

Cooperative efforts between IP and EDA vendors are the most efficient way to achieve compliance with standards and ensure that the IP can be successfully embedded and verified in the target chip. QualCore Logic, Magma Design Automation and Denali Software have recently finished preparing QualCore Logic's soft PCI Express Controller core for implementation in chips using Magma's design tools and design flow along with Denali's verification software. The process the companies went through is a good illustration of the type of cooperation IP and EDA providers need to have to simplify the overall task of the system-on-chip designer. This is particularly important due to a lack of standardization regarding IP deliverables from vendor to user. Without adequate standards covering IP delivery, the chip designer must find out from the vendor what the vendor has done to a particular core so that it reliably meets specifications and can be used within the customer's design flow for a given design.

PCI Express is set to replace current I/O interfaces such as PCI for device interconnects and AGP8X for graphics on a variety of PCs and servers. To successfully implement the PCI core in silicon, Magma worked closely with QualCore to take the V6210 PCI Express controller through the Magma-Ready IP support process. The cooperative effort included verifying compatibility with the PCI Express standard as well as integration of cell libraries and other IPs used with the core along with EDA tools and design flows.

Through this close collaboration the companies were able to quickly identify and implement changes to the core. For example, some of the coding styles in the PCI Express core were changed to optimize the hardware description language code. In addition, with the Magma synthesis flow, QualCore did not need to overconstrain the block, which allowed QualCore to reduce synthesis time and achieve timing closure faster. Overconstraining a design at the synthesis stage and hoping to meet timing is a common practice for front-end designers using traditional EDA tools from other vendors. Blast Create, Magma's unified front-end design environment, lets the designer accurately constrain the design to get the desired performance without having to leave performance on the table.

See related chart Cooperative efforts between IP and EDA vendors are the most efficient way to achieve compliance with standards and ensure that the IP can be successfully embedded and verified in the target chip. QualCore, Magma and Denali Software cooperated on QualCores soft PCI Express Controller core. Source: Qualcore Logic

Blast Create comprises logic synthesis, physical synthesis, design-for-test (DFT) analysis and insertion, power optimization, and static-timing analysis. The soft PCI Express core verified by Magma had to support industry-standard Verilog and VHDL formats; popular synthesis programs; formal verification and timing-validation requirements; and include correct scripts and documentation for design optimization with the core in Magma's RTL-to-GDSII design flow. Cooperative efforts were needed to ensure a clean handoff between the IP customer's front-end RTL designer and back-end layout engineer, eliminating time-consuming and expensive back-to-front iterations for design timing closure (see figure).

With core verification a critical part of successful design with the QualCore PCI Express core, Magma worked with Denali, a design- and verification-IP provider, to ensure that Denali understood and could support the Magma-Ready IP support process. This established working relationship made it easier to address IP implementation issues; for the PCI Express core, there were none. IP users use Denali's PureSpec verification IP to validate PCI Express compliance at the HDL level. PureSpec gives designers a modeling and verification environment that ensures full compliance and optimal performance of the QualCore IP. PureSpec supports all PCI Express protocol layers (physical, data link and transaction); models for all device types (including the root complex, switch, endpoint and PCI Express to PCI bridge); programmable data/traffic generation; error injection and detection; and extensible assertions, callbacks and call-forwards.

Using PureSpec, the designer can answer functional coverage questions relating to exercising all bus operations, exercising all data bits, hitting all possible configurations and states, and whether there were any timing or protocol violations. Complementing PureSpec is PureSuite, Denali's comprehensive interface verification suite. PureSuite exercises designs and measures compliance with industry-standard complex interface specifications like PCI Express, and interoperability with other designs utilizing such interfaces.

Through cooperative efforts, QualCore, Magma and Denali have already done most of the work to assure design flow compatibility and PCI Express compliance. The cooperation gives designers using the QualCore PCI Express core a total design and verification environment for implementing PCI Express-based SoCs. This is the type of solution that IP customers should demand. The coupling between silicon cores and chip design tools is only becoming more complex with shrinking technology nodes and increasing chip complexity, making cooperation between IP providers and EDA vendors an even bigger necessity over time.

Mahendra Jain (mjain@qualcorelogic.com) is president and chief executive officer of QualCore Logic Inc. (Sunnyvale, Calif.) and Michael Ma (mma@magma-da.com) is vice president of business development at Magma Design Automation Inc. (Santa Clara, Calif.).