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Electronic system-level approach shortens SoC design
(02/14/2008 11:00 AM EST) -- EE Times The main reason for designing systems-on-chip at the electronic system level is to reduce time-to-market, development cost and power consumption. A widespread approach to system- level design is the application of virtual platforms, which are typically specified in executable languages such as C, C++ or SystemC. These platforms represent abstract models of SoCs containing only information about system behaviors of interest to systems designers, such as data about the functional behavior of the system together with transaction-level communication. Virtual platforms are used chiefly to aid early software development for embedded cores and to refine the final architecture of SoCs. Architectural refinements under various constraints, such as performance or power consumption, can be carried out much more easily and quickly using an abstract, compact system-level description than with a register transfer-level (RTL) description. The designer has less code to deal with at the system level, and simulation and analysis of the timing and power of the run-times used to compare design alternatives are much shorter. Typical system architecture refinements in- clude hardware/software partitioning, intellectual-property block selection, bus structure definition, memory hierarchy definition and power management strategy. The design decisions made for these refinements at the ESL profoundly affect the power consumption and energy requirements of resulting SoCs and are in fact a main concern for system design teams. It is therefore important to look at ways to analyze and optimize designs at the ESL in light of energy and power consumption requirements.
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