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How to design FPGA-based advanced PCI Express endpoint solutionsBy Doug Kern, Xilinx October 16, 2006 -- pldesignline.com The state of the PCI Express protocol Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, enterprise, mobile, workstation, networking, communications, industrial control, and medical equipment markets. With more than 58 form factors, including Express Card, Advanced TCA, Compact PCI Express, Com Express, and a cable spec, the PCIe protocol is becoming ubiquitous. The PCI Special Interest Group (PCI-SIG) maintains the PCIe specification (along with the PCI and PCI-X specifications) and holds compliance workshops. The PCIe subsystem is a point-to-point interface that replaces and overcomes the limitations of bus-based PCI and PCI-X standards. PCIe Generation 1 (Gen1) offers 2.5 gigabits per second (Gbps) speed with low-voltage differential signaling (LVDS), embedded 8B/10B encoding, dual-simplex signaling, and message-based serial protocol. With plans in place to increase bandwidth to 5 Gbps in Generation 2 and 10 Gbps in Generation 3, the PCIe bus is expected to be the dominant high-bandwidth interconnect for several years to come. (For more information on the PCIe specification or compliance information, visit www.PCISIG.com.) With scaleable lane widths from ×1 to ×32 lanes and advanced features such as traffic classes, virtual channels, hot-plug, and power management, the PCIe interface provides support for a wide range of applications – ranging from a simple upgrade from PCI to an ×1 PCIe endpoint device to advanced high-bandwidth ×8 PCIe communications endpoint devices. Fig 1 shows the topology of a sample PCIe system. The CPU is connected to a root device and is responsible for configuring and enumerating all plug-and-play PCI Express endpoint devices in a system. Because the PCIe system is point-to-point, switch devices are necessary to grow the number of devices or endpoints in a system. A switch has one "upward-facing" port and numerous "downward-facing" ports. These downward facing ports connect to the working devices or endpoints of a system.  1. PCI Express system topology. Although only one root exists in any system, there are one or more endpoint devices. For example, a standard PC motherboard provides three to seven expansion PCIe slots. The numerous value-added endpoint designs are the largest target application for the FPGA-based designs.
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