Headline (February 2008) Sign Up for SoC News Alert  |
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Articles for the Week of Feb. 28, 2008
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Featured Article
Improving design turn around time on a complex SoC by leveraging a reusable low power specification
This paper presents an approach to power design specification intent and associated enabled design methodologies that allow a scalable implementation of voltage islands. |
Additional Articles |
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Dual Mode SMIA/MIPI Receiver Supporting 2Gbps |
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Power mode technologies verify today's SoCs |
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Multicore systems-on-chip can handle embedded designs |
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Complex SoC Testing with a Core-Based DFT Strategy |
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TI's MSP430 vs. ST Microelectronics' ARM Cortex-based processor for battery-powered apps |
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Signal Processing on the MIPS 74K |
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Articles for the Week of Feb. 21, 2008
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Featured Article
Secure Your Security Key in On-Chip SRAM: Techniques to avoid Data Remanance Attacks
Security protection in modern microcontroller’s logic devices with memories is based on the assumption that information from the memory disappears completely after erasing or when the power to the memory is removed. |
Additional Articles |
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Comparing IP integration approaches for FPGA implementation |
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Enhanced Capacitor Cross Coupled Front-End |
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ARM provides the microcontroller solution |
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Infusing Speed and Visibility Into ASIC Verification |
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Multi-language Functional Verification Coverage for Multi-site Projects |
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Articles for the Week of Feb. 14, 2008
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Featured Article
Building High-Quality, Mixed-Signal IP in 65-nm and Beyond
This paper presents some key concepts necessary to design and build high-quality mixed-signal IP in 65‑nm or smaller geometries. The paper addresses design, layout, and verification techniques—with a focus on low-power design, reliability, and yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property (MSIP) portfolio. |
Additional Articles |
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Designing digital video broadcast and wireless systems with common FPGA building blocks |
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Electronic system-level approach shortens SoC design |
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IPGenius, an on-line IP generation platform |
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Simplifying PLL Design |
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How to manage a billion cycles |
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Hardware design using ESL |
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Fast virtual platforms open up multicore software development |
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Articles for the Week of Feb. 07, 2008
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Featured Article
Accelerating High-Level SysML and SystemC SoC Designs
The goal of this research is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling techniques that should result in modeling both the structure and behavioral SysML diagram to produce a single executable that represents the system behavior. A prototype for a translation tool, a SysML model compiler, has been implemented using a UML editing tool that supports SysML. |
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Software - The X factor |
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Using nextgen PCI Express switches to eliminate network I/O bottlenecks |
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Understanding the LIN PHY (physical) layer |
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Putting the system in electronic system design |
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DSPs vs. FPGAs for multiprocessing |
