Headline (January 2008) Sign Up for SoC News Alert  |
 | |
| |
| |
|
Articles for the Week of Jan. 31, 2008
|
| |
| |
| |
Featured Article
Mixed Signal Drivers for Ultra Low Power and Very High Power Applications
Evolving niche markets, such as ICs for biomedical applications, are very challenging in respect to power consumption and on chip power dissipation, namely, wide range from ultra low power (ULP) functionality (<uW) where IC is battery powered, e.g. mobile micro transducers, to very high power (VHP, >5W), e.g. coded energy transfer from RFID¡¯s for remote sensing and animal tracking. |
Additional Articles |
| |
|
UWB Time-interleaved ADC exploiting SAR |
| |
|
FPGA-Based Prototyping - "Productivity to Burn" |
| |
|
For smoother embedded systems development, design-out the hardware |
| |
|
Analog IP: The changing technology scene |
| |
| |
|
Articles for the Week of Jan. 24, 2008
|
| |
| |
| |
Featured Article
Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)
This paper presents challenges with the synchronous (clocked) designs and describes the techniques to overcoming the same with asynchronous (Clockless) design methodology. The paper proposes to redesign the synchronous interconnect to an asynchronous interconnect that should cater to tomorrow’s needs of high speed and low power. These circuits work on Handshaking techniques. If not today SOC industry will be forced driven to this methodology tomorrow. |
Additional Articles |
| |
|
FPGAs tackle microcontroller tasks: Part 2 - 'Flexible' CPUs |
| |
|
How to achieve timing-closure in high-end FPGAs |
| |
|
Automated Formal Verification of OCP based IPs using Cadence's OCP VIP library |
| |
|
FPGAs tackle microcontroller tasks: Part 1 - Application growth strains architecture and ASICs |
| |
| |
|
Articles for the Week of Jan. 17, 2008
|
| |
| |
| |
Featured Article
A Chip IP Integrator for System Level Design
This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. This paper shares the approach, methodology and the results on a real-life system comprising several RTL design blocks in Verilog each having around a quarter of million instances as well as on an ARM 4 CPU test chip design. |
Additional Articles |
| |
|
To develop or buy a Verification IP |
| |
|
Analysis: ZSP800 and VZ.AudioHD platform |
| |
|
RF integration: Full SoC, or just a SiP? |
| |
|
FPGA design and verification using Simulink |
| |
| |
|
Articles for the Week of Jan. 10, 2008
|
| |
| |
| |
Featured Article
H.264 Baseline Decoder With ADI Blackfin DSP and Hardware Accelerators
In this paper, architecture and implementation of H.264/AVC baseline decoder for D1 resolution at 30fps using ADI Blackfin DSP and Hardware accelerators in FPGA is described. |
Additional Articles |
| |
|
USB Host IP-Core Hardware and Software Concurrent Development |
| |
|
OCP VIP: A cost effective and robust qualification process for multimedia and telecom SoC designs |
| |
|
Dealing with the challenges of integrating hardware and software verification |
| |
|
The art of FPGA construction |
| |
|
Why we need an analog design flow that's like digital now |
| |
| |
|
Articles for the Week of Jan. 02, 2008
|
| |
| |
| |
Featured Article
Automated Test-Bench for Mobile Applications
This paper describes the design and implementation of an Automated Test-Bench Application for Mobile phones that can advance the complete development cycle of application development and validate the robustness of the solution. |
| |
|
Verification Platform for Complex Designs |
| |
|
Understanding Clock Domain Crossing Issues |
| |
|
Achieving higher performance in a multicore-based packet processing engine design |
